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7620797 Instructions for efficiently accessing unaligned vectors  
One embodiment of the present invention provides a processor which is configured to execute load-swapped instructions, which are possibly directed to unaligned source address. The processor is...
7620787 Optimizing memory accesses for network applications using indexed register files  
A processing device includes an optimizer to migrate objects from an external memory of a network processing to local memory device to registers connected to a processor. The optimizer further...
7610466 Data processing system using independent memory and register operand size specifiers and method thereof  
Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of...
7587535 Data transfer control device including endian conversion circuit with data realignment  
When data is transferred to an access destination in a different endian format, a transfer start address is aligned based on a transfer bus width, and a transfer size is adjusted according to the...
7587532 Full/selector output from one of plural flag generation count outputs  
A method and apparatus for adaptive buffer sizing adjusts the size of the buffer at different levels using a “high water mark” to different levels for different system conditions. The high...
7577777 Computer system providing endian information and method of data transmission thereof  
A computer system providing endian information and a method of data transmission thereof are disclosed. The method of data transmission in the computer system of the present invention comprises:...
7568070 Instruction cache having fixed number of variable length instructions  
A fixed number of variable-length instructions are stored in each line of an instruction cache. The variable-length instructions are aligned along predetermined boundaries. Since the length of each...
7565510 Microprocessor with a register selectively storing unaligned load instructions and control method thereof  
A load/store unit includes a Top register for storing a value retained before loading to a load destination register and a saved register capable of storing data retained to the Top register. When...
7525457 Transforming design objects in a computer by converting data sets between data set types  
A computer implemented method converts a data set of a first type to a data set type of a second type. The method includes casting up a first data set of a first type to a prescribed data set type...
7480783 Systems for loading unaligned words and methods of operating the same  
Disclosed are systems for loading an unaligned word from a specified unaligned word address in a memory, the unaligned word comprising a plurality of indexed portions crossing a word boundry, a...
7473293 Processor for executing instructions containing either single operation or packed plurality of operations dependent upon instruction status indicator  
A conversion table converts a packed instruction (pre-conversion code) contained in the instruction code fetched from an instruction memory into a plurality of instruction codes (converted codes)....
7467327 Method and system of aligning execution point of duplicate copies of a user program by exchanging information about instructions executed  
A method and system of aligning execution point of duplicate copies of a user program by exchanging information about instructions executed. At least some of the exemplary embodiments may be a...
7444488 Method and programmable unit for bit field shifting  
A method and a programmable unit for bit field shifting in a memory device in a programmable unit as a result of the execution of an instruction, in which a bit segment is shifted within a first...
7437537 Methods and apparatus for predicting unaligned memory access  
In an instruction execution pipeline, the misalignment of memory access instructions is predicted. Based on the prediction, an additional micro-operation is generated in the pipeline prior to the...
7412584 Data alignment micro-architecture systems and methods  
Systems and methods are disclosed for aligning data in memory access and other applications. In one embodiment a system is provided that includes a memory unit, a shifter, and control logic...
7404042 Handling cache miss in an instruction crossing a cache line boundary  
A fetch section of a processor comprises an instruction cache and a pipeline of several stages for obtaining instructions. Instructions may cross cache line boundaries. The pipeline stages process...
7404019 Method and apparatus for endianness control in a data processing system  
A method for providing endianness control in a data processing system includes initiating an access which accesses a peripheral, providing a first endianness control that corresponds to the...
7392366 Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetches  
A multithreaded processor, fetch control for a multithreaded processor and a method of fetching in the multithreaded processor. Processor event and use (EU) signs are monitored for downstream...
7386706 System and software for matched aligned and unaligned storage instructions  
A system and software for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions in an instruction set comprising (a) group...
7360059 Variable width alignment engine for aligning instructions based on transition between buffers  
In one embodiment, a digital signal processor includes look ahead logic to decrease the number of bubbles inserted in the processing pipeline. The processor receives data containing instructions in...
7353371 Circuit to extract nonadjacent bits from data packets  
A method and device to copy data fields from one or more source packets to one or more result packets. In a SET function, adjacent data fields in a source packet is copied to respective destination...
7343473 System and method for translating non-native instructions to native instructions for processing on a host processor  
A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning...
7334066 Computer system providing endian information and method of data transmission thereof  
A computer system providing endian information and a method of data transmission thereof are disclosed. The method of data transmission in the computer system of the present invention comprises:...
7328433 Methods and apparatus for reducing memory latency in a software application  
Methods and apparatus for reducing memory latency in a software application are disclosed. A disclosed system uses one or more helper threads to prefetch variables for a main thread to reduce...
7305542 Instruction length decoder  
Speculatively decoding instruction lengths in order to increase instruction throughput. Instructions are speculatively decoded within a pipelined microprocessor architecture such that up to four...
7302552 System for processing VLIW words containing variable length instructions having embedded instruction length identifiers  
A processor is described including a plurality of data path elements which independently perform in parallel different data processing operations. Program instructions are provided which are...
7296108 Apparatus and method for efficient transmission of unaligned data  
An apparatus and method to transmit unaligned data over an interface bus while providing the appearance of aligned data transfers to the receiving processor. In a preferred embodiment, an alignment...
7293177 Preventing virus infection in a computer system  
A method of preventing an electronic file containing a computer virus from infecting a computer system using the Symbian™ operating system, the method comprising the steps of scanning files using...
7275147 Method and apparatus for data alignment and parsing in SIMD computer architecture  
Execution of a single stand-alone instruction manipulates two n bit strings of data to pack data or align the data. Decoding of the single instruction identifies two registers of n bits each and a...
7272675 First-in-first-out (FIFO) memory for buffering packet fragments through use of read and write pointers incremented by a unit access and a fraction of the unit access  
Disclosed is an apparatus and method used in an interface for scheduling the store-forwarding of back-to-back multi-channel packet fragments, comprising a first-in-first-out (FIFO) memory, a read...
7249352 Apparatus and method for removing elements from a linked list  
Methods, apparatus and computer program products for removal of elements from a linked list while other elements of the linked list are allowed to be accessed during the removal operation. In one...
7234045 Apparatus and method for handling BTAC branches that wrap across instruction cache lines  
A branch control apparatus in a microprocessor. The apparatus includes a branch target address cache (BTAC) that caches indications of whether a branch instruction wraps across two cache lines....
7222225 Programmable processor and method for matched aligned and unaligned storage instructions  
A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions in an instruction set...
7213129 Method and system for a two stage pipelined instruction decode and alignment using previous instruction length  
A system and method for aligning an instruction stream is described. The system comprises a rotator logic unit for rotating data bytes of the instruction stream. A shifter logic unit is used for...
7210023 Data processing apparatus and method for moving data between registers and memory in response to an access instruction having an alignment specifier identifying an alignment to be associated with a start address  
The present invention provides a data processing apparatus and method for performing aligned access operations. The data processing apparatus comprises a register data store having a plurality of...
7203824 Apparatus and method for handling BTAC branches that wrap across instruction cache lines  
A branch control apparatus in a microprocessor. The apparatus includes a branch target address cache (BTAC) that caches indications of whether a branch instruction wraps across two cache lines....
7203636 Endian transformation  
A method for emulating a processor of a first endian type on a processor of a second endian type, wherein each memory access address B of string length L is transformed to the address A−B−L+S,...
7181562 Wired endian method and apparatus for performing the same  
A method and associated apparatus is provided for operating an electronic device in accordance with a wired endian format. More specifically, the wired endian format requires multi-byte values be...
7134001 Pipeline replay support for unaligned memory operations  
Instructions asserted in a microprocessors instruction pipeline ( 3 ) are accompanied by control information, comprising a group of bits, asserted within a control information pipeline ( 5 ) that...
7134000 Methods and apparatus for instruction alignment including current instruction pointer logic responsive to instruction length information  
An instruction alignment unit for aligning instructions in a digital processor having a pipelined architecture includes an instruction queue, a current instruction buffer and a next instruction...
7107584 Data alignment between native and non-native shared data structures  
Described herein is a technology facilitating the operation of non-native program modules within a native computing platform. This technology provides a mechanism for aligning—as...
7089393 Data processing using a coprocessor  
A data processing system using a main processor 8 and a coprocessor 10 provides coprocessor load instructions (USALD) for loading a variable number of data values dependent upon alignment into...
7082516 Aligning instructions using a variable width alignment engine having an intelligent buffer refill mechanism  
In one embodiment, a digital signal processor includes look ahead logic to decrease the number of bubbles inserted in the processing pipeline. The processor receives data containing instructions in...
7051168 Method and apparatus for aligning memory write data in a microprocessor  
There is provided a method for aligning and inserting data elements into a memory based upon an instruction sequence consisting of one or more alignment instructions and a single store instruction....
7047396 Fixed length memory to memory arithmetic and architecture for a communications embedded processor system  
A method and system for fixed-length memory-to-memory processing of fixed-length instructions. Further, the present invention is a method and system for implementing a memory operand width...
6996735 Apparatus for alignment of data collected from multiple pipe stages with heterogeneous retention policies in an unprotected pipeline  
A method and apparatus for trace data alignment for trace data generated during differing instruction pipeline stages selectively delays write data, memory access address and memory access control...
6996678 Method and apparatus for randomized cache entry replacement  
A cache controller is disclosed. The cache controller includes potential replacement list, a plurality of valid bits and a number of counters. The potential replacement list includes a number of...
6981127 Apparatus and method for aligning variable-width instructions with a prefetch buffer  
A method and apparatus for providing a plurality of aligned instructions from an instruction stream provided by a memory unit for execution within a pipelined microprocessor is described. The...
6978359 Microprocessor and method of aligning unaligned data loaded from memory using a set shift amount register instruction  
An aspect of the present invention provides a method of processing unaligned data in a microprocessor including, storing a first part of the unaligned data in a first register, storing a second...
6966056 Processor for making more efficient use of idling components and program conversion apparatus for the same  
A processor that has a plurality of instruction slots each of which stores an instruction to be executed in parallel. One of the plurality of instruction slots is a first instruction slot and...
Matches 1 - 50 out of 205 1 2 3 4 5 >