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9015622 Profile-based performance tuning of computing systems  
Some embodiments of a system and a method to tune a computing system based on a profile have been presented. A profile as used herein broadly refers to a file containing various parameters of a...
9013717 ***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***
Handheld imaging device with multi-core image processor integrating common bus interface and dedicated image sensor interface
 
A handheld imaging device includes an image sensor for sensing an image; a multi-core processor for processing the sensed image; and a program memory provided external to the multi-core processor,...
8996278 Control device for internal combustion engine  
In a control device for an internal combustion engine, which includes control unit that has a processor with a plurality of cores and that computes various tasks associated with operation of the...
8990767 Parallelization method, system and program  
A method, system, and article of manufacture for solving ordinary differential equations described in a graphical model with nodes as blocks and dependencies as links using the processing of a...
8966491 System and method for implementing NUMA-aware reader-writer locks  
NUMA-aware reader-writer locks may leverage lock cohorting techniques to band together writer requests from a single NUMA node. The locks may relax the order in which the lock schedules the...
8954497 Parallel distributed processing method and computer system  
Provided is a parallel distributed processing method executed by a computer system comprising a parallel-distributed-processing control server, a plurality of extraction processing servers and a...
8880485 Systems and methods to facilitate multi-threaded data retrieval  
According to some embodiments, a data source is accessed from which data will be retrieved via a plurality of processing threads. The data source may have, for example, a plurality of records with...
8862839 Storage system and storage management method for controlling off-line mode and on-line mode of flash memory  
A storage system which has flash memories constituting a storage area and a function of placing and handling the flash memories in on-line mode and off-line mode, and which stores and manages...
8799884 Software application performance enhancement  
Generating parallelized executable code from input code includes statically analyzing the input code to determine aspects of data flow and control flow of the input code; dynamically analyzing the...
8682998 Method and server cluster for map reducing flow services and large documents  
The present invention refers to a method for MapReducing the processing of an Electronic Data Interchange (EDI) document (1, the method comprising the following steps: a. mapping the EDI document...
8665458 Image forming apparatus including a control unit that generates print data by carrying out a rasterizing process based on a display list, and computer readable recording medium  
Disclosed is an image forming apparatus which generates print data based on control data for page print inputted from an external device and which forms an image based on the print data. The image...
8650384 Method and system for dynamically parallelizing application program  
Provided is a method and system for dynamically parallelizing an application program. Specifically, provided is a method and system having multi-core control that may verify a number of available...
8638805 Packet draining from a scheduling hierarchy in a traffic manager of a network processor  
Described embodiments provide for restructuring a scheduling hierarchy of a network processor having a plurality of processing modules and a shared memory. The scheduling hierarchy schedules...
8624910 Register indexed sampler for texture opcodes  
One embodiment of the present invention sets forth a technique for dynamically specifying a texture header and texture sampler using an index. The index corresponds to a particular register value...
8619312 Image processing apparatus for allocating job data for rip processing, image processing method for allocating job data for rip rocessing, and computer-readable storage medium  
An image processing apparatus includes: a receiving unit that receives job data of plural pages; plural RIP processors that interpret and expand the job data into raster images; and an allocating...
8619800 Parallel processing using multi-core processor  
Disclosed are methods, systems, paradigms and structures for processing data packets in a communication network by a multi-core network processor. The network processor includes a plurality of...
8423605 Parallel distributed processing method and computer system  
Provided is a parallel distributed processing method executed by a computer system comprising a parallel-distributed-processing control server, a plurality of extraction processing servers and a...
8347272 Call graph dependency extraction by static source code analysis  
A method of analyzing program source code prepared for a multithreading platform comprises analyzing a targeted source code set to extract a set of characteristic information for each wait...
8296524 Supporting efficient spin-locks and other types of synchronization in a cache-coherent multiprocessor system  
Some embodiments of the present invention provide a system that acquires a lock in a shared memory multiprocessor system. During operation, the system loads the lock into a cache associated with...
8275917 Efficient communication of producer/consumer buffer status  
A mechanism is provided for efficient communication of producer/consumer buffer status. With the mechanism, devices in a data processing system notify each other of updates to head and tail...
8245207 Technique for dynamically restricting thread concurrency without rewriting thread code  
A method for executing uniprocessor (UP) coded workloads in a computer capable of concurrent thread execution is disclosed. The method identifies threads in the uniprocessor coded workloads...
8239847 General distributed reduction for data parallel computing  
General-purpose distributed data-parallel computing using high-level computing languages is described. Data parallel portions of a sequential program written in a high-level language are...
8214808 System and method for speculative thread assist in a heterogeneous processing environment  
A system and method for speculative assistance to a thread in a heterogeneous processing environment is provided. A first set of instructions is identified in a source code representation (e.g., a...
8205204 Apparatus and method for scheduling threads in multi-threading processors  
An multi-threading processor is provided. The multi-threading processor includes a first instruction fetch unit to receive a first thread and a second instruction fetch unit to receive a second...
8179896 Network processors and pipeline optimization methods  
A network processor of an embodiment includes a packet classification engine, a processing pipeline, and a controller. The packet classification engine allows for classifying each of a plurality...
8127121 Apparatus for executing programs for a first computer architechture on a computer of a second architechture  
Executing programs coded in an instruction set of a first computer on a computer of a second, different architecture. An operating system maintains an association between each one of a set of...
8078804 Method and arrangement for cache memory management, related processor architecture  
A data cache memory coupled to a processor including processor clusters are adapted to operate simultaneously on scalar and vectorial data by providing data locations in the data cache memory for...
8069337 Methods and apparatus for dynamic instruction controlled reconfigurable register file  
A scalable reconfigurable register file (SRRF) containing multiple register files, read and write multiplexer complexes, and a control unit operating in response to instructions is described....
8015567 Advanced processor with mechanism for packet distribution at high line rate  
An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores...
7954095 Analysis and selection of optimal function implementations in massively parallel computer  
An apparatus, program product and method optimize the operation of a parallel computer system by, in part, collecting performance data for a set of implementations of a function capable of being...
7941802 Reduced instruction set for java virtual machines  
Techniques for implementing virtual machine instructions suitable for execution in virtual machines are disclosed. The inventive virtual machine instructions can effectively represent the complete...
7941648 Methods and apparatus for dynamic instruction controlled reconfigurable register file  
A scalable reconfigurable register file (SRRF) containing multiple register files, read and write multiplexer complexes, and a control unit operating in response to instructions is described....
7853937 Object-oriented, parallel language, method of programming and multi-processor computer  
This invention relates to architecture and synchronization of multi-processor computing hardware. It establishes a new method of programming, process synchronization, and of computer construction,...
7822948 Apparatus, system, and method for discontiguous multiple issue of instructions  
An apparatus, system, and method are disclosed for discontiguous multiple issue of instructions. An assignment unit assigns a plurality of instruction blocks to a plurality of issue units. The...
7810084 Parallel generating of bundles of data objects  
Computer-implemented methods, computer systems and computer program products are provided for parallel processing a plurality of data objects with a plurality of processors. As disclosed herein,...
7810083 Mechanism to emulate user-level multithreading on an OS-sequestered sequencer  
Method, apparatus and system embodiments to provide user-level creation, control and synchronization of OS-invisible “shreds” of execution via an abstraction layer for a system that includes one...
7788670 Performance-based workload scheduling in multi-core architectures  
Systems and methods of managing workloads provide for detecting a workload for a system having a first processor core with a first performance indicator and a second processor core with a second...
7779244 Multi-socket boot  
In some embodiments, the invention involves a system and method to provide maximal boot-time parallelism for future multi-core, multi-node, and many-core systems. In an embodiment, the security...
7746347 Methods and systems for processing a geometry shader program developed in a high-level shading language  
Methods and systems for processing a geometry shader program developed in a high-level shading language are disclosed. Specifically, in one embodiment, after having received the geometry shader...
7739647 Methods and system for configurable domain specific abstract core  
The present invention provides a configurable domain specific abstract core (DSAC) for implementing applications within any domain. The DSAC comprises at least one function specific abstract...
7689820 Rapid-boot computing device with dual operating systems  
A computing device is booted in a manner that enables a software application to begin execution with minimal delay. When the device is powered up, a first processor system begins booting under...
7657883 Instruction dispatch scheduler employing round-robin apparatus supporting multiple thread priorities for use in multithreading microprocessor  
A dispatch scheduler in a multithreading microprocessor is disclosed. Each of N concurrently executing threads has one of P priorities. P N-bit round-robin vectors are generated, each being a...
7657880 Safe store for speculative helper threads  
The latencies associated with retrieving instruction information for a main thread are decreased through the use of a simultaneous helper thread. The helper thread is permitted to execute Store...
7650331 System and method for efficient large-scale data processing  
A large-scale data processing system and method includes one or more application-independent map modules configured to read input data and to apply at least one application-specific map operation...
7649862 Flexible through-connection process in a mobile switch center when multiple outgoing call legs involved  
The flexible through-connection process, operational in a Mobile Switch Center, that provides support for allowing the call routing processor of the Mobile Switch Center to independently perform a...
7647593 Image processing system for volume rendering  
A CPU 111m segments the jobs from each of the volume rendering processing on hand, prioritize processing sequence for each job, transmits one job which has reached the processing order to the...
7516323 Security management system in parallel processing system by OS for single processors  
On a parallel processing system which operates an OS and an existing application for single processors on a multiprocessor to realize parallel processing by the multiprocessor with respect to the...
7509484 Handling cache misses by selectively flushing the pipeline  
An apparatus and method for efficiently managing data cache load misses is described in connection with a multithreaded, pipelined multiprocessor chip. A CMT processor keeps track of load misses...
7500240 Apparatus and method for scheduling threads in multi-threading processors  
An multi-threading processor is provided. The multi-threading processor includes a first instruction fetch unit to receive a first thread and a second instruction fetch unit to receive a second...
7493448 Prevention of conflicting cache hits without an attendant increase in hardware  
A multiprocessor system includes a plurality of processors that share a multiple-way set-associative cache memory that includes a directory and a data array, the multiprocessor system being...

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