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7516323 |
Security management system in parallel processing system by OS for single processors
On a parallel processing system which operates an OS and an existing application for single processors on a multiprocessor to realize parallel processing by the multiprocessor with respect to the...
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7509484 |
Handling cache misses by selectively flushing the pipeline
An apparatus and method for efficiently managing data cache load misses is described in connection with a multithreaded, pipelined multiprocessor chip. A CMT processor keeps track of load misses...
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7500240 |
Apparatus and method for scheduling threads in multi-threading processors
An multi-threading processor is provided. The multi-threading processor includes a first instruction fetch unit to receive a first thread and a second instruction fetch unit to receive a second...
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7493448 |
Prevention of conflicting cache hits without an attendant increase in hardware
A multiprocessor system includes a plurality of processors that share a multiple-way set-associative cache memory that includes a directory and a data array, the multiprocessor system being...
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7484076 |
Executing an SIMD instruction requiring P operations on an execution unit that performs Q operations at a time (Q<P)
Methods, apparatuses, and systems are presented for performing instructions using multiple execution units in a graphics processing unit involving issuing an instruction for P executions of the...
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7475397 |
Methods and apparatus for providing a remote serialization guarantee
A technique provides a remote serialization guarantee within a computerized system. The technique involves (i) receiving a serialization command from a first thread running on a first processor of...
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7436559 |
Load assignment in image processing by parallel processing
In image processing carried out by means of repeated execution of process set which includes N unit processes (where N is an integer equal to 3 or greater), prior to execution of the process...
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7404048 |
Inter-cluster communication module using the memory access network
An inter-cluster communication module using the memory access network is provided, including a plurality of clusters, a memory subsystem, a controller and a switch device. When some clusters issue...
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7395412 |
Apparatus and method for extending data modes in a microprocessor
An apparatus and method are provided for extending a microprocessor instruction set beyond its current capabilities to allow for extended size operands specifiable by programmable instructions in...
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7395408 |
Parallel execution processor and instruction assigning making use of group number in processing elements
The parallel execution processor 100 fetches a piece of instruction data. When the piece of instruction data includes only one instruction, the instruction decoding unit 120 assigns the one...
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7373640 |
Technique for dynamically restricting thread concurrency without rewriting thread code
The present invention provides a technique for converting a multi-threaded application configured to execute on a uniprocessor (UP) system to one that executes on a multiprocessor (MP) system....
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7302551 |
Suppression of store checking
An apparatus and method are provided for extending a microprocessor instruction set to allow for selective suppression of store checking at the instruction level. The apparatus includes fetch...
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7302548 |
System and method for communicating in a multi-processor environment
A method for communicating in a multi-processor environment is provided that includes generating a bit at an originating processor associated with a message to be communicated to a destination...
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7249352 |
Apparatus and method for removing elements from a linked list
Methods, apparatus and computer program products for removal of elements from a linked list while other elements of the linked list are allowed to be accessed during the removal operation. In one...
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7243333 |
Method and apparatus for creating and executing integrated executables in a heterogeneous architecture
The present invention provides a compilation system for compiling and linking an integrated executable adapted to execute on a heterogeneous parallel processor architecture. The compiler and linker...
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7225431 |
Method and apparatus for setting breakpoints when debugging integrated executables in a heterogeneous architecture
The present invention provides inserting and deleting a breakpoint in a parallel processing system. A breakpoint is inserted in a module loaded into the execution environment of an attached...
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7222332 |
Method and apparatus for overlay management within an integrated executable for a heterogeneous architecture
The present invention provides for creating and employing code and data partitions in a heterogeneous environment. This is achieved by separating source code and data into at least two partitioned...
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7152124 |
Method and system for maintaining temporal consistency of resources and data in a multiple-processor packet switch
A network switch architected using multiple processor engines includes a method and system for ensuring temporal consistency of data and resources as packet traffic flows through the switch. Upon...
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7137109 |
System and method for managing access to a controlled space in a simulator environment
In one embodiment, the invention may comprise a computer-implemented system for managing access to a controlled space in a simulator environment, comprising: means for requiring initialization of a...
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7111132 |
Parallel processing apparatus, system, and method utilizing correlated data value pairs
An apparatus may include a first storage location to store a key value of an activated correlated data values (CDV) pair and a second storage location to store a correlated value corresponding to...
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7096344 |
Processor for improving instruction utilization using multiple parallel processors and computer system equipped with the processor
The present invention provides a processor capable of carrying out a plurality of operation instructions simultaneously in one cycle which improves utilization of an instruction when carrying out a...
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7080362 |
Java virtual machine hardware for RISC and CISC processors
A hardware Java™ accelerator is provided to implement portions of the Java™ virtual machine in hardware in order to accelerate the operation of the system on Java™ bytecodes. The Java™...
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7079147 |
System and method for cooperative operation of a processor and coprocessor
A disclosed coprocessor receives a user-defined command during execution of an instruction including the user-defined command, and performs a predetermined function in response to the user-defined...
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7073048 |
Cascaded microcomputer array and method
A microcomputer array and method having a hyper-scalable, real-time monitoring and debug architecture in which several microcomputers are cascaded together into a single, more powerful unit. A...
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7000051 |
Apparatus and method for virtualizing interrupts in a logically partitioned computer system
A resource and partition manager virtualizes interrupts without using any additional hardware in a way that does not disturb the interrupt processing model of operating systems running on a logical...
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6976249 |
Method for embedding object codes in source codes
Methods for embedding codes executable in a first system having a first microprocessor into codes executable in a second system having a second microprocessor are described herein. In one aspect of...
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6940864 |
Network access traffic sorter
Packetized voice, video, and data traffic (data frames) are received in a communication traffic sorter. The data frames have a dispatch priority corresponding to their transmission characteristics...
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6922736 |
Computer system and data processing method
A computer system has a node and a service processor (SVP) connected together via a diagnosis section. An input/output (I/O) unit is connected to the SVP. The diagnosis section has a serial...
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6912647 |
Apparatus and method for creating instruction bundles in an explicitly parallel architecture
An apparatus and method for creating instruction groups for explicitly parallel architectures is provided. The apparatus and method accept instruction groups as input and determine a number of each...
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6877084 |
Central processing unit (CPU) accessing an extended register set in an extended register mode
A central processing unit (CPU) is described including a register file and an execution core coupled to the register file. The register file includes a standard register set and an extended...
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6842728 |
Time-multiplexing data between asynchronous clock domains within cycle simulation and emulation environments
An apparatus and method utilize a buffer interposed in a common signal path between asynchronous clock domains in a hardware-based logic emulation environment to manage the communication of...
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6834385 |
System and method for utilizing dispatch queues in a multiprocessor data processing system
A method for utilizing dispatch queues operates in a data processing system that has multiple processors, an operating system, and an application with multiple threads. According to that method, a...
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6785892 |
Communications between partitioned host processors and management processor
An inventive protocol for communicating between a management processor and host processors allows for the cooperative management of resources among host processors within a partition and also among...
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6763449 |
Operation-processing apparatus
An operation-processing apparatus is equipped with an instruction decoder for decoding an existing instruction and an extension instruction into the same operation code including at least...
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6745384 |
Anticipatory optimization with composite folding
A method and system for anticipatory optimization of computer programs. The system generates code for a program that is specified using programming-language-defined computational constructs and...
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6745320 |
Data processing apparatus
There is provided a data processing apparatus capable of increasing a number of general purpose registers while maintaining upper compatibility. Register designating information for designating a...
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6704833 |
Atomic transfer of a block of data
A method for transferring data between a processor and a memory includes (A) executing, at the processor, an instruction that includes (i) a specifier of a location in a storage resource local to...
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6681317 |
Method and apparatus to provide advanced load ordering
An apparatus and method to provide ordering when an advanced load address table is used for advanced loads. An advanced load address table (ALAT) is used to retain an entry associated with a...
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6564313 |
System and method for efficient instruction prefetching based on loop periods
The invention contemplates a system and method for efficient instruction prefetching based on the termination of loops. A computer system may be contemplated herein, wherein the computer system may...
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6564179 |
DSP emulating a microcontroller
The present invention provides a processor device and technique having the capability of providing a two-processor solution with only one processor. In accordance with the principles of the present...
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6532487 |
Method and system for managing semaphores in an object-oriented multi-tasking computer system
A semaphore manager data structure for managing semaphores in a multi-tasking computer system is disclosed. The data structure comprises of a multiple of indices corresponding to each class, a...
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6516403 |
System for synchronizing use of critical sections by multiple processors using the corresponding flag bits in the communication registers and access control register
A hardware arrangement for implementing synchronization control between multiple processors is disclosed. The hardware arrangement is provided with a plurality of communication registers which are...
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6477638 |
Synchronized instruction advancement through CPU and FPU pipelines
A computer system having a central processing unit (CPU) execution pipeline and a floating point unit (FPU) execution pipeline, the CPU pipeline including a plurality of pipestages and the FPU...
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6466988 |
Multiprocessor synchronization and coherency control system
A shared main memory type multiprocessor is arranged to have a switch connection type. The multiprocessor prepares an instruction for outputting a synchronization transaction. When each CPU...
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6424870 |
Parallel processor
A parallel processor system has a plurality of nodes interconnected by a network for communication under control of a network interface controller of each node. The network interface controller...
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6353829 |
Method and system for memory allocation in a multiprocessing environment
A method and system for allocating memory. The computer system on which the memory allocation system executes may support the simultaneous execution of multiple threads. Under control of a thread,...
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6314485 |
Automatic status register
One aspect of the present invention provides a packer-unpacker (PUP) for a digital serial interface which allows a plurality of processors to access time slot registers of a serial data stream...
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6311265 |
Apparatuses and methods for programming parallel computers
A system provides an environment for parallel programming by providing a plurality of modular parallelizable operators stored in a computer readable memory. Each operator defines operation...
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6249787 |
Method and apparatus for transmitting images and other objects over a computer network system
A network browsing system includes a host computer coupled to a client computer by a network. A network browser process implemented on the client computer is capable of establishing a connection...
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6223275 |
Microprocessor with reduced instruction set limiting the address space to upper 2 Mbytes and executing a long type register branch instruction in three intermediate instructions
A 32-bit RISC processor is disclosed. The bit length of the instruction set is fixed to 16 bits. SLIL and SLIH instructions that cause the address space of 4 Gbytes to be limited to upper 2 Mbytes...
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