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9015622 Profile-based performance tuning of computing systems  
Some embodiments of a system and a method to tune a computing system based on a profile have been presented. A profile as used herein broadly refers to a file containing various parameters of a...
8966461 Vector width-aware synchronization-elision for vector processors  
A medium, method, and apparatus are disclosed for eliding superfluous function invocations in a vector-processing environment. A compiler receives program code comprising a width-contingent...
8930677 Computer operation control method, program, and system  
A computer implemented control method, article of manufacture, and computer implemented system for determining whether stack allocation is possible. The method includes: allocating an object...
8918622 Computer operation control method, program and system  
A computer implemented control method, article of manufacture, and computer implemented system for determining whether stack allocation is possible. The method includes: allocating an object...
8788796 Technique for simulating floating-point stack operation involving conversion of certain floating-point register numbers based on a top-of-stack pointer and modulo function  
A Reduced Instruction Set Computing (RISC) processor is capable of emulating operation of a floating-point register stack. The RISC processor may include a floating-point register file containing...
8638805 Packet draining from a scheduling hierarchy in a traffic manager of a network processor  
Described embodiments provide for restructuring a scheduling hierarchy of a network processor having a plurality of processing modules and a shared memory. The scheduling hierarchy schedules...
8627267 Apparatus and method for initializing system global variables by using multiple load/store instructions  
An apparatus and method for initializing system global variables by using a multiple load/store instruction is disclosed. The apparatus includes: a first storing unit for storing a system global...
8458441 Vector extensions to an interpreted general expression evaluator in a database system  
The subject disclosure is directed towards technology by which an expression in a database engine is executed against stacks of data. Each instruction of the expression is evaluated against the...
8429634 Semiconductor device, memory circuit, and machine language program generation device, and method for operating semiconductor device and memory circuit  
A semiconductor device has an arithmetic processing circuit provided with an arithmetic circuit and a control circuit and a memory circuit provided with a ROM and a RAM, where the arithmetic...
8234476 Information processing apparatus and method of updating stack pointer  
A instruction execution part of an information processing device outputs an access request including a first address information to specify an access destination based on an execution of an access...
8234516 Topology collection method and dual control board device for a stacking system  
The invention provides a topology collection method and dual control board device applicable to a stacking system comprising dual control board devices. A master control board of a dual control...
8195885 Electronic unit for saving state of task to be run in stack  
In an electronic unit having a stack in memory and adapted to run a plurality of tasks in accordance with a multitask operating system and to save context data in the stack, a scheduling unit...
8179540 Image forming apparatus and management system utilizing counter and job log information for usage tracking  
An image forming apparatus is provided that holds counter information obtained by integrating a consumption of a consumable that depends on usage of service provided by the image forming...
7979685 Multiple instruction execution mode resource-constrained device  
A resource-constrained device comprises a processor configured to execute multiple instruction streams comprising multiple instructions having an opcode and zero or more operands. Each of the...
7975127 Computer system for processing instructions each containing a group of operations to be executed out of order  
A computer system comprising a data file having entries each of which is designed to hold data, an advanced and a completed mapping file each having entries each of which is designed to hold a...
7900027 Scalable link stack control method with full support for speculative operations  
A computer implemented method, a processor chip, a computer program product, and a data processing system managing a link stack. The data processing system utilizes speculative pushes onto and...
7840782 Mixed stack-based RISC processor  
A processor (e.g., a co-processor) executes a stack-based instruction set and another instruction in a way that accelerates the execution of the stack-based instruction set, although code...
7805573 Multi-threaded stack cache  
Systems and methods for storing stack data for multi-threaded processing in a specialized cache reduce on-chip memory requirements while maintaining low access latency. An on-chip stack cache is...
7784057 Single-stack model for high performance parallelism  
A method and apparatus are provided for operating a processor. The method comprising the steps of providing a single call stack for execution of a plurality of tasks that operate on the processor,...
7752427 Stack underflow debug with sticky base  
A stack pointer is copied to a stack pointer base to debug stack underflow. A move instruction, used to initialize the stack pointer, is modified to additionally copy the stack pointer to a stack...
7743377 Cooperative threading in a managed code execution environment  
A runtime execution environment may manage resources executing cooperative threading on a single physical thread. One example can scan eligible activation records linked to threads on a method...
7685406 Determination of current stack pointer value using architectural and speculative stack pointer delta values  
A technique for reducing stack pointer adjustment operations when stack dependent operations, which correspond to stack dependent instructions, are encountered includes setting a stack pointer to...
7617383 Circular register arrays of a computer  
A stack processor comprises a data stack with a T register, an S register, and eight hardwired bottom registers which function in a circular repeating pattern. The stack processor also comprises a...
7590823 Method and system for handling an instruction not supported in a coprocessor formed using configurable logic  
Method of informing a processor that a coprocessor instruction is not executable by a coprocessor is described. The coprocessor, instantiated in configurable logic, is configured to execute a...
7539849 Maintaining a double-ended queue in a contiguous array with concurrent non-blocking insert and remove operations using a double compare-and-swap primitive  
An array-based concurrent shared object implementation has been developed that provides non-blocking and linearizable access to the concurrent shared object. In an application of the underlying...
7496734 System and method for handling register dependency in a stack-based pipelined processor  
There is disclosed a data processor comprising 1) a register stack comprising a plurality of architectural registers that stores operands required by instructions executed by the data processor;...
7447875 Method and system for management of global queues utilizing a locked state  
A method and system for managing global queues is provided. In one example, a method for implementing a global queue is provided. The queue has a head pointer, a tail pointer, and zero or more...
7424596 Code interpretation using stack state information  
Executing an instruction on an operand stack, including performing a stack-state aware translation of the instruction to threaded code to determine an operand stack state for the instruction,...
7415602 Apparatus and method for processing a sequence of jump instructions  
An apparatus for processing a sequence of instructions, which comprises a LCALL instruction, a FCALL instruction and a common re-jump instruction (return), comprises a means for reading-in an...
7406592 Method, system, and apparatus for efficient evaluation of boolean expressions  
Methods, systems, and computer-readable media are provided for efficiently evaluation Boolean expressions. According to the method, the Boolean expression is expressed using pre-fix notation. Each...
7380245 Technique for detecting corruption associated with a stack in a storage device  
A technique for detecting corruption associated with a stack in a storage device is disclosed. In one embodiment, the technique is realized by having a processing device insert a quantity of...
7363475 Managing registers in a processor to emulate a portion of a stack  
The present invention is generally directed to method and apparatus for emulating a portion of a stack. Certain embodiments of the invention manage a plurality of processor registers to store the...
7350059 Managing stack transfers in a register-based processor  
The present invention is generally directed to a method and apparatus for emulating a portion of a stack. Certain embodiments of the invention manage data transfers between processor registers...
7340592 Executing a translated block of instructions and branching to correction code when expected top of stack does not match actual top of stack to adjust stack at execution time to continue executing without restarting translating  
A method of generating an expected TOS during translation of instructions. The method includes translating a first block of instructions executable in a first processor architecture, into a...
7302550 Stack of variable length operands and method for use  
An operand stack (10) permits optimization of memory space and a continuous check of operand type by creating a type memory (20) which stores type information for each operand, said information...
7296271 Replaceable scheduling algorithm in multitasking kernel  
Disclosed is providing one of a plurality of schedulers for a multitasking system for a processor that includes choosing a particular one of the schedulers, setting a program counter to an address...
7228532 Method and apparatus to facilitate code verification and garbage collection in a platform-independent virtual machine  
One embodiment of the present invention provides a system that facilitates code verification and garbage collection in a platform-independent virtual machine. The system operates by first...
7210134 Deterring reverse-engineering of software systems by randomizing the siting of stack-based data  
A given software process is composed on one or more threads of execution. Each thread possesses its own stack, a region of memory set aside by the operating system for that thread to store data....
7191313 Microprocessor  
The present invention provides a microprocessor which enables task switching with a small time overhead. Upon reception of input of an interrupt control signal during execution of a task-1, a...
7136990 Fast POP operation from RAM cache using cache row value stack  
A method and apparatus for performing a fast pop operation from a random access cache is disclosed. The apparatus includes a stack onto which is pushed the row and way of push instruction data...
7131118 Write-through caching a JAVA® local variable within a register of a register bank  
In a data processing apparatus 2 having a first mode of operation in which JAVA® bytecodes 46, 48 specify the processing operations and a second mode of operation in which other instructions...
7124288 Programmable unit with a stack buffer storage device configurable into discrete shadow storage elements accessible by a plurality of command execution units  
A programmable unit includes a command execution unit for carrying out commands, a memory device for storing data required for command execution and data emitted from the command execution unit,...
7120775 Inter-procedural allocation of stacked registers for a processor  
A method for an allocation of stacked registers for Intel's Itanium® processor includes a three step process. Step I determines an intra-procedural stacked register usage by a program having a...
7085914 Methods for renaming stack references to processor registers  
According to one aspect of the invention, there is provided a method for renaming memory references to stack locations in a computer processing system. The method includes the steps of detecting...
7080239 Loop control circuit and loop control method  
A loop control circuit and a loop control method that allow control on multiplexed loop operations to be executed with less overhead are provided. A loop control circuit comprises a means for...
7080236 Updating stack pointer based on instruction bit indicator without executing an update microinstruction  
A stack pointer update technique in which the stack pointer is updated without executing micro-operations to add or subtract a stack pointer value. The stack pointer update technique is also...
7073049 Non-copy shared stack and register file device and dual language processor structure using the same  
The present invention provides a non-copy shared stack and register set device and a dual language processor structure using the same, which achieve non-copy data sharing by controlling a selector...
7055133 Method and apparatus for eliminating C recursion from a Java programming language bytecode interpreter  
Methods and apparatus for eliminating C recursion from interpreter loops are disclosed. According to one aspect of the present invention, a computer-implemented method for substantially...
7028163 Apparatus for controlling multi-word stack operations using a multi-bank stack in digital data processors  
A digital data processor comprising a stack storage having a plurality of locations classified into two or more banks, and a stack pointer circuit pointing to one or more stack banks of the stack...
7024537 Data speculation based on addressing patterns identifying dual-purpose register  
A system may include a memory file and an execution core. The memory file may include an entry configured to store an addressing pattern and a tag. If an addressing pattern of a memory operation...

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