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7613902 |
Device and method for enabling efficient and flexible reconfigurable computing
A power-efficient, distributed reconfigurable computing system and method are provided. A reconfigurable computing system may include an embedded controller for performing real-time control and...
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7606943 |
Adaptable datapath for a digital processing system
The present invention includes a adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN...
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7503051 |
Broadcast data receiving device and method for receiving a plurality of multimedia data
A data distribution system is provided which generates outputs attribute data about multimedia data in advance and broadcasts the output attribute data together with the multimedia data so that the...
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7493469 |
Performance evaluation apparatus, performance evaluation method, program and computer readable recording medium
From an application program described in the form of a flow graph, input and output arcs are extracted. Packet rates on the input and output arcs are extracted, and it is determined whether the...
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7415595 |
Data processing without processor core intervention by chain of accelerators selectively coupled by programmable interconnect network and to memory
A programmable digital signal processor includes a plurality of memory units, a plurality of accelerator units and a processor core. The digital signal processor also includes a programmable...
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7409533 |
Asynchronous communication among hardware object nodes in IC with receive and send ports protocol registers using temporary register bypass select for validity information
Embodiments of the invention are directed to an integrated circuit including a communication network that interconnects individual object nodes. The nodes include a receiving port and a sending...
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7406584 |
IC comprising network of microprocessors communicating data messages along asynchronous channel segments using ports including validity and accept signal registers and with split / join capability
Embodiments of the invention are directed to a communication network on an integrated circuit for a number of interconnected microprocessors. The network is made from a number of sending nodes and...
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7398329 |
Pipelined I/O execution
A method for pipelining execution input/output (I/O) includes obtaining a first I/O operation, determining a first plurality of stages of a pipeline needed to execute the first I/O operation, and...
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7386636 |
System and method for communicating command parameters between a processor and a memory flow controller
A system and method for communicating command parameters between a processor and a memory flow controller are provided. The system and method make use of a channel interface as the primary...
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7353516 |
Data flow control for adaptive integrated circuitry
The present invention concerns data flow control in adaptive integrated circuitry which utilizes a data flow model for data processing. The present invention controls task initiation and execution...
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7251721 |
Conditional link pointer register sets marking the beginning and end of a conditional instruction block where each set corresponds to a single stage of a pipeline that moves link pointers through each corresponding register of said register sets as instructions move through the pipeline
For use in a wide-issue processor, a mechanism for, and method of, conditionally executing instructions and a digital signal processor (DSP) incorporating the mechanism or the method. In one...
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7240347 |
Systems and methods for preserving the order of data
A device includes an input processing unit and an output processing unit. The input processing unit dispatches first data to one of a group of processing engines, records an identity of the one...
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7225319 |
Digital architecture for reconfigurable computing in digital signal processing
A digital embedded architecture, includes a microcontroller and a memory device, suitable for reconfigurable computing in digital signal processing and comprising: a processor, structured to...
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7174525 |
Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip
An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines...
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7143266 |
Storing immediate data of immediate instructions in a data table
An efficient coding scheme is disclosed. The coding provides for the separation of immediate data from the instruction stream. A static flow analysis determines the immediate data in the program...
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7114008 |
Edge adapter architecture apparatus and method
An architecture for intercepting and processing packets from a network is disclosed. The architecture provides both stateful and stateless processing of packets in the bi-directional network flow....
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7085850 |
Stateless message processing scheme for network processors interactions
A stateless message-passing scheme for interactions between a network processor and a coprocessor is provided. The network processor, when receiving data frames for transmission from a network...
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7062762 |
Partitioning symmetric nodes efficiently in a split register file architecture
The present invention provides methods specifically geared to finding natural splits in wide, nearly symmetric dependence graphs and assigning the components of the split to clusters in a VLIW...
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7051186 |
Selective bypassing of a multi-port register file
A multi-port register file may be selectively bypassed such that any element in a result vector is bypassed to the same index of an input vector of a succeeding operation when the element is...
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7035996 |
Generating data type token value error in stream computer
A stream computer comprises a plurality of interconnected functional units. The functional units are responsive to a data- stream containing data and tokens. The data is to be operated on by one or...
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7000098 |
Passing a received packet for modifying pipelining processing engines' routine instructions
In one embodiment, a method is provided. The method of this embodiment includes generating, by a processor that includes a plurality of processing engines capable of executing program instructions,...
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6993639 |
Processing instruction addressed by received remote instruction and generating remote instruction to respective output port for another cell
Embodiments of the invention relate to a processing cell for use in computing systems. Generally, a processing cell generates remote instructions to be received and processed by at least one other...
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6976150 |
Resource flow computing device
A scalable processing system includes a memory device having a plurality of executable program instructions, wherein each of the executable program instructions includes a timetag data field...
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6970996 |
Operand queue for use in a floating point unit to reduce read-after-write latency and method of operation
A floating point unit includes floating point processing units for executing floating point instructions that write operands to an external memory and for executing floating point instructions that...
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6954843 |
Data driven information processor capable of internally processing data in a constant frequency irrespective of an input frequency of a data packet from the outside
A packet generation unit divides a plurality of generated clocks to generate clocks with different frequencies, selects any of the frequencies, sets destination information and data depending on a...
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6941448 |
Data-driven processor having multiple-precision data processing function and data processing method thereof
When a prescribed operation is performed on 1024-bit multiple-precision data in a data-driven processor, the multiple-precision data is treated as a plurality of single-precision data obtained by...
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6934938 |
Method of programming linear graphs for streaming vector computation
A method for producing a formatted description of a computation representable by a data-flow graph and computer for performing a computation so described. A source instruction is generated for each...
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6904512 |
Data flow processor
A data flow processor includes a number of hardware units each having more than one mode. A plurality of hardware units may be connected together to implement a flow made up of a series of...
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6889310 |
Multithreaded data/context flow processing architecture
Multithreaded data- and context-flow processing is achieved by flowing data and context (thread) identification tokens through specialized cores (functional blocks, intellectual property). Each...
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6874079 |
Adaptive computing engine with dataflow graph based sequencing in reconfigurable mini-matrices of composite functional blocks
Aspects of a method and system for digital signal processing within an adaptive computing engine are described. These aspects include a mini-matrix, the mini-matrix comprising a set of composite...
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6839889 |
Mixed hardware/software architecture and method for processing xDSL communications
A method of implementing a scaleable architecture for a communications system is disclosed, based on minimizing a total gate count for the communications system to reduce cost, complexity, etc. The...
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6823443 |
Data driven type apparatus and method with router operating at a different transfer rate than system to attain higher throughput
A router is formed by an M-input, 1-output junction unit and a 1-input, N-output branching unit. Where M and N satisfy the relation of (M>N), the transfer rate of a path between the junction...
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6745320 |
Data processing apparatus
There is provided a data processing apparatus capable of increasing a number of general purpose registers while maintaining upper compatibility. Register designating information for designating a...
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6742107 |
Dynamically configured processing of composite stream input data using next conversion determining state transition table searched by converted input data
A table storing a state transition rule is arranged in a memory. By referencing the table based on input data, the process to be performed for the input data is determined and executed....
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6728862 |
Processor array and parallel data processing methods
An array of processor elements has multiple instruction streams and multiple data streams broadcast to all of the processor elements. The processor elements are each connected to multiple...
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6708272 |
Information encryption system and method
An encryption system permits end-to-end encryption of information over an untrusted interconnection network. The information encryption system includes at least one client for processing...
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6675285 |
Geometric engine including a computational module without memory contention
A method and apparatus for eliminating memory contention in a computation module is presented. The method includes, for a current operation being performed by a computation engine of the...
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6658550 |
Pipelined asynchronous processing
An asynchronous processor having pipelined instruction fetching and execution to implement concurrent execution of instructions by two or more execution units. A writeback unit is connected to...
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6631462 |
Memory shared between processing threads
A method includes pushing a datum onto a stack by a first processor and popping the datum off the stack by a second processor.
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6594815 |
Asynchronous controller generation method
A method for generating an asynchronous controller includes a process controller formation step S 100 of forming a signal transition graph representing a state of change in input/output signals of...
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6526500 |
Data driven type information processing system consisting of interconnected data driven type information processing devices
The data driven type information processing system has a branch unit and a junction unit in the input and output stages thereof, and includes a plurality of data driven type processors between the...
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6519693 |
Method and system of program transmission optimization using a redundant transmission sequence
A system and method of optimizing transmission of a program to multiple users over a distribution system, with particular application to video-on-demand for a CATV network. The system includes, at...
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6516402 |
Information processing apparatus with parallel accumulation capability
An initial value of read address is set in a first initial address register; an initial value of write address is set in a second initial address register; and the number of data to be accumulated...
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6505291 |
Processor having a datapath and control logic constituted with basis execution blocks
A processor is provided with a datapath and control logic, where the datapath and/or the control logic are constituted with basis execution blocks (BEB). Each BEB includes an addressable storage...
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6493818 |
Technique for pipelining synchronization to maintain throughput across two asynchronous clock domain boundaries
This invention is a data synchronous apparatus for synchronization between a first clock domain to a second clock domain asynchronous with the first clock domain. This invention provides for...
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6460129 |
Pipeline operation method and pipeline operation device to interlock the translation of instructions based on the operation of a non-pipeline operation unit
A pipeline operation method and a pipeline operation device in which an operation result of an operation unit can be effectively written to a register. In the pipeline operation method and the...
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6449711 |
Method, apparatus, and article of manufacture for developing and executing data flow programs
Methods, systems, and articles of manufacture consistent with the present invention provide a development tool that enables computer programmers to design and develop a data flow program for...
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6442672 |
Method for dynamic allocation and efficient sharing of functional unit datapaths
The invention is a processing method and a processor architecture which contains multiple processors on the same silicon but which does not make a fixed compromise by statically assigning...
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6434692 |
High-throughput interface between a system memory controller and a peripheral device
A high-throughput memory access interface allows higher data transfer rates between a system memory controller and video/graphics adapters than is possible using standard local bus architectures....
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6425068 |
UNIT FOR PROCESSING NUMERIC AND LOGIC OPERATIONS FOR USE IN CENTRAL PROCESSING UNITS (CPUS), MULTIPROCESSOR SYSTEMS, DATA-FLOW PROCESSORS (DSPS), SYSTOLIC PROCESSORS AND FIELD PROGRAMMABLE GATE ARRAYS (EPGAS)
An expanded arithmetic and logic unit (EALU) with special extra functions is integrated into a configurable unit for performing data processing operations. The EALU is configured by a function...
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