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7620803 |
Data processing device and electronic equipment using pipeline control
A data processing device is provided using pipeline architecture to reduce a time loss due to a branch without causing an increase in circuit scale. The data processing device uses pipeline...
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7620798 |
Latency tolerant pipeline synchronization
A synchronization mechanism is used to synchronize events across multiple execution pipelines that process transaction streams. A common set of state configuration is included in each transaction...
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7610475 |
Programmable logic configuration for instruction extensions
A processing system with reconfigurable instruction extensions includes a processor, programmable logic, a register file, and a load/store module. The processor executes a computer program...
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7590823 |
Method and system for handling an instruction not supported in a coprocessor formed using configurable logic
Method of informing a processor that a coprocessor instruction is not executable by a coprocessor is described. The coprocessor, instantiated in configurable logic, is configured to execute a...
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7584343 |
Data reordering processor and method for use in an active memory device
An active memory device includes a command engine that receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a...
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7584150 |
Recording method, recording medium, and recording system
An information recording medium and an optical recording system allow target information (such as an ad) to be displayed without requiring changes in hardware or physical specifications. The...
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7571300 |
Modular distributive arithmetic logic unit
A memory system includes a plurality of memory blocks, each having a dedicated local arithmetic logic unit (ALU). A data value having a plurality of bytes is stored such that each of the bytes is...
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7562209 |
Supporting different instruction set architectures during run time
A platform may use heterogeneous instruction set architectures which may be called during run time. Using a system table, an operating system may be directed to the appropriate services for any of...
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7543288 |
Reduced instruction set for Java virtual machines
Techniques for implementing virtual machine instructions suitable for execution in virtual machines are disclosed. The inventive virtual machine instructions can effectively represent the complete...
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7533246 |
Application program execution enhancing instruction set generation for coprocessor and code conversion with marking for function call translation
A method for automatically configuring a microprocessor architecture so that it is able to efficiently exploit instruction level parallelism in a particular application. Executable code for another...
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7500084 |
Multifunction hexadecimal instruction form
A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the...
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7487331 |
Programming a digital processor with a single connection
A digital processor may be coupled to a processor programmer through a single conductor programming bus. The digital processor and the processor programmer, each may have a single programming...
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7478223 |
Symbol parsing architecture
A devices and method for parsing a data stream comprises a parser stack configured to store one or more parsing symbols, each parsing symbol representing a different state of data stream parsing, a...
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7464252 |
Programmable processor and system for partitioned floating-point multiply-add operation
A programmable processor and system for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying three registers each...
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7454570 |
Efficient memory update process for on-the-fly instruction translation for well behaved applications executing on a weakly-ordered processor
A multiprocessor data processing system (MDPS) with a weakly-ordered architecture providing processing logic for substantially eliminating issuing sync instructions after every store instruction of...
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7450131 |
Memory layout for re-ordering instructions using pointers
Embodiments include storing graphics instructions at addresses in a memory in an original order, and storing in the memory pointers associated with each instruction pointing to the addresses of the...
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7444488 |
Method and programmable unit for bit field shifting
A method and a programmable unit for bit field shifting in a memory device in a programmable unit as a result of the execution of an instruction, in which a bit segment is shifted within a first...
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7437536 |
Systems and methods for task migration
Methods and systems are provided whereby, in one aspect, pointers to address locations of instructions, static data and dynamically-created data are stored such that the instructions, static data...
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7434028 |
Hardware stack having entries with a data portion and associated counter
According to some embodiments, determining a new value to be pushed onto a hardware stack having n entries is determined. Each entry in the stack may include a data portion and an associated...
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RE40509 |
Methods and apparatus for abbreviated instruction sets adaptable to configurable processor architecture
An improved manifold array (ManArray) architecture addresses the problem of configurable application-spacific instruction set optimization and instruction memory reduction using an instruction...
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7415596 |
Parser table/production rule table configuration using CAM and SRAM
A system and method for parsing a data stream comprises a production rule table populated with production rules, a parser table populated with production rule codes that correspond to production...
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7415042 |
System and method for dynamic information retrieval using a state machine
A system and method for retrieving information from a frame. A plurality of entries is initialized in a translation table. The translation table has a plurality of rows. Each of the plurality of...
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7409532 |
Method and apparatus for extending operations of an application in a data processing system
A method, an apparatus, and computer instructions are provided for extending operations of an application in a data processing system. A primary operation is executed. All extended operations of...
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7406584 |
IC comprising network of microprocessors communicating data messages along asynchronous channel segments using ports including validity and accept signal registers and with split / join capability
Embodiments of the invention are directed to a communication network on an integrated circuit for a number of interconnected microprocessors. The network is made from a number of sending nodes and...
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7403835 |
Device and method for programming an industrial robot
In a device and method for programming an industrial robot using a simulation program, control commands are issued by a handheld programming device and these commands are visualized on an image...
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7398276 |
Parallel predictive compression and access of a sequential list of executable instructions
Compression and decompression of data such as a sequential list of executable instructions (e.g., program binaries) by uniformly applying a predictive model generated from one segment of the...
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7395411 |
Methods and apparatus for improving processing performance by controlling latch points
Methods and apparatus provide for performing pre-execution processes to prepare instructions of an instruction set for further processing; executing the instructions in a pipeline of execution...
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7395082 |
Method and system for handling events in an application framework for a wireless device
Methods and systems for application framework development for wireless devices are provided herein. Aspects of the method may include acquiring an MMI event from an MMI event queue within the MMI...
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7392344 |
Data-processing system and method for supporting varying sizes of cache memory
A data-processing system and method include a processor core associated with a cache controller. A plurality of cached memory components is associated with the processor core and the cache...
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7383425 |
Massively reduced instruction set processor
This invention is directed to a method and apparatus for providing low, predictable latencies in processing IP packets. The apparatus provides a specialized microprocessor or hardwired circuitry to...
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7380105 |
Prediction based instruction steering to wide or narrow integer cluster and narrow address generation
A method and apparatus for improving the operation of a computer processor by utilizing an asymmetric clustered processor architecture are disclosed. The asymmetric clustered processor apparatus...
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7376807 |
Data processing system having address translation bypass and method therefor
In a data processing system a processor including processing logic performs data processing. An address translator that is coupled to the processing logic performs address translation and a method...
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7373143 |
Adaptive radio patch interface system
The present invention is directed to an RF communications system that includes a first radio processor module having a first receiver portion programmed to convert a first analog receive signal...
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7353516 |
Data flow control for adaptive integrated circuitry
The present invention concerns data flow control in adaptive integrated circuitry which utilizes a data flow model for data processing. The present invention controls task initiation and execution...
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7353337 |
Reducing cache effects of certain code pieces
Cache memory interrupt service routines (ISRs) influence the replacement of necessary instructions of the instruction stream they interrupt; it is known as “instruction cache washing,” since...
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7346430 |
Image transmission device and method, transmitting device and method, receiving device and method, and robot apparatus
An image transmission device and method, a transmitting device and method, a receiving device and method, and robot apparatus are capable of effectively transmitting the image data of multiple...
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7343479 |
Method and apparatus for implementing two architectures in a chip
The present invention is a method for implementing two architectures on a single chip. The method uses a fetch engine to retrieve instructions. If the instructions are macroinstructions, then it...
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7340591 |
Providing parallel operand functions using register file and extra path storage
A number of architectural and implementation approaches are described for using extra path (Epath) storage that operate in conjunction with a compute register file to obtain increased instruction...
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7340589 |
Shift prefix instruction decoder for modifying register information necessary for decoding the target instruction
The data processing device and electronic equipment of the present invention perform pipeline control and include a fetch circuit which fetches instruction codes of a plurality of instructions in...
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7340587 |
Information processing apparatus, microcomputer, and electronic computer
An information processing apparatus performing pipeline control includes a first fetch cue fetching a non-branch location instruction, a second fetch cue fetching a branch location instruction, a...
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7322032 |
Methods and apparatus for scheduling operation of a data source
A computerized device has dynamically modifiable hardware, such as an ASIC, that performs queue-scheduling operations. The hardware incorporates a generic sorting processor (GSP) that is...
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7313672 |
Intellectual property module for system-on-chip
Disclosed is an IP module for an SOC which brings easiness in designing system architecture and integration. The IP module of the invention includes a controller for generating a control signal for...
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7313646 |
Interfacing of functional modules in an on-chip system
An electronic system comprises an initiator module and a target module addressable by the initiator module, and an interface and control module for interfacing between respective communication...
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7308561 |
Fast, scalable pattern-matching engine
A fast and scalable pattern making engine is presented. The engine represents variations on a Shift-And method capable of matching patterns in data streams having high speed data rates. In one...
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7305541 |
Compression of program instructions using advanced sequential correlation
Compressing program binaries with reduced compression ratios. One or several pre-processing acts are performed before performing compression using a local sequential correlation oriented...
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7302550 |
Stack of variable length operands and method for use
An operand stack ( 10 ) permits optimization of memory space and a continuous check of operand type by creating a type memory ( 20 ) which stores type information for each operand, said information...
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7299341 |
Embedded system with instruction prefetching device, and method for fetching instructions in embedded systems
In a method for fetching instructions in an embedded system, a predicted one of a set of the instructions stored in a memory device is fetched and is subsequently stored in an instruction buffer...
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7293177 |
Preventing virus infection in a computer system
A method of preventing an electronic file containing a computer virus from infecting a computer system using the Symbian™ operating system, the method comprising the steps of scanning files using...
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7284114 |
Video processing system with reconfigurable instructions
A video processing system with reconfigurable instructions includes a processor, a first register file in the processor, an extension adapter, programmable logic, a second register file coupled to...
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7257665 |
Branch-aware FIFO for interprocessor data sharing
A branch aware first-in first-out (FIFO) memory may include a memory array to store data; a push pointer to address memory locations therein to write data; a pop pointer to address memory locations...
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