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7515899 Distributed grid computing method utilizing processing cycles of mobile phones  
Additional computing power is captured using the idle processing power of mobile phones incorporated into a grid computing system, wherein the system is capable of pushing projects out to available...
7487302 Service layer architecture for memory access system and method  
A memory subsystem includes a memory controller operable to generate first control signals according to a standard interface. A memory interface adapter is coupled to the memory controller and is...
7467286 Executing partial-width packed data instructions  
A method and apparatus are provided for executing packed data instructions. According to one aspect of the invention, a processor includes registers, a register renaming unit coupled to the...
7457938 Staggered execution stack for vector processing  
In one embodiment, the present invention includes a method for executing an operation on low order portions of first and second source operands using a first execution stack of a processor and...
7441098 Conditional execution of instructions in a computer  
A method of executing instructions in a computer system on operands containing a plurality of packed objects in respective lanes of the operand is described. Each instruction defines an operation...
7418575 Long instruction word processing with instruction extensions  
A system for adding reconfigurable computational instructions to a computer, the system comprising a processor operable to execute a set of instructions of a computer program comprising a set of...
7404066 Active memory command engine and method  
A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array...
7401333 Array of parallel programmable processing engines and deterministic method of operating the same  
The present invention provides an array of parallel programmable processing engines interconnected by a switching network. At least some of the processing engines execute a thread, and at least...
7392329 System and method for applying an action initiated for a portion of a plurality of devices to all of the plurality of devices  
In accordance with one embodiment of the present invention, a method of applying an action initiated for a portion of a plurality of devices to all of the plurality of devices is provided. The...
7383427 Multi-scalar extension for SIMD instruction set processors  
A method is provided for executing a plurality of parallel executable sequences of instructions on a processor having a plurality of execution units operated by a single instruction unit. The...
7360005 Software programmable multiple function integrated circuit module  
An electrically programmable multiple selectable function integrated circuit module has a plurality of optionally selectable function circuits, which receive and manipulate a plurality of input...
7313646 Interfacing of functional modules in an on-chip system  
An electronic system comprises an initiator module and a target module addressable by the initiator module, and an interface and control module for interfacing between respective communication...
7035991 Surface computer and computing method using the same  
A surface computer includes an address generator for generating an address for adjusting surface region data concerning at least a storage region and a concurrent computer, provided at a subsequent...
7028107 Process for automatic dynamic reloading of data flow processors (DFPS) and units with two- or three- dimensional programmable cell architectures (FPGAS, DPGAS, and the like)  
A system for communication between a plurality of functional elements in a cell arrangement and a higher-level unit is described. The system may include, for example, a configuration memory...
6944744 Apparatus and method for independently schedulable functional units with issue lock mechanism in a processor  
A functional unit of a processor may be configured to operate on instructions as either a single, wide functional unit or as multiple, independent narrower units. For example, an execution unit may...
6928535 Data input/output configuration for transfer among processing elements of different processors  
An image input section and a signal processing section are provided. The image input section includes an array of pixel in which a plurality of pixels having a CMOS type photoelectric converting...
6925548 Data processor assigning the same operation code to multiple operations  
A data processor can assign a greater number of operations to instruction codes with shorter length, thereby implementing high performance, high code efficiency and low cost data processor. The...
6848041 Methods and apparatus for scalable instruction set architecture with dynamic compact instructions  
A hierarchical instruction set architecture (ISA) provides pluggable instruction set capability and support of array processors. The term pluggable is from the programmer's viewpoint and relates to...
6839828 SIMD datapath coupled to scalar/vector/address/conditional data register file with selective subpath scalar processing mode  
There is provided a processor designed to operate in a plurality of modes for processing vector and scalar instructions. Register files are each for storing scalar and vector data and address...
6785800 Single instruction stream multiple data stream processor  
A SIMD processor includes plural processor elements (PEs) each having a processing unit for data processing, a register for holding data to be processed or already processed by the processing unit,...
6785799 Multiprocessor with asynchronous pipeline processing of instructions, and control method thereof  
A multiprocessor includes M banks storing a plurality of instructions; and N processors each having N instruction fetch stages, wherein each of the N processors processes one of the plurality of...
6782463 Shared memory array  
Disclosed is a device comprising a core processing circuit coupled to a single memory array which is partitioned into at least a first portion as a cache memory of the core processing circuit, and...
6775766 Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor  
A ManArray processor pipeline design addresses an indirect VLIW memory access problem without increasing branch latency by providing a dynamically reconfigurable instruction pipeline for SIWs...
6772368 Multiprocessor with pair-wise high reliability mode, and method therefore  
In one embodiment a multiprocessing apparatus includes a first processor and a second processor. Each of the processors have their own data and instruction caches to support independent operation....
6766437 Composite uniprocessor  
Instruction and data registers of processors of a multiprocessing computing system are joined and forked to allow processing in multiple modes of operation. When joined, the registers of the...
6684318 Intermediate-grain reconfigurable processing device  
A programmable integrated circuit utilizes a large number of intermediate-grain processing elements which are multibit processing units arranged in a configurable mesh. The coarse-grain resources,...
6643763 Register pipe for multi-processing engine environment  
Method, system and program storage device are provided for implementing a register pipe between processing engines of a multiprocessor computing system. A register pipe includes at least one first...
6618698 Clustered processors in an emulation engine  
Clusters of processors are interconnected as an emulation engine such that processors share input and data stacks, and the setup and storing of results are done in parallel, but the output of one...
6581152 Methods and apparatus for instruction addressing in indirect VLIW processors  
An indirect VLIW (iVLIW) architecture is described which contains a minimum of two instruction memories. The first instruction memory (SIM) contains short-instruction-words (SIWs) of a fixed...
6553479 Local control of multiple context processing elements with major contexts and minor contexts  
A method and apparatus for providing local control of processing elements in a network of multiple context processing element are provided. A multiple context processing element is configured to...
6526461 Interconnect chip for programmable logic devices  
A method and apparatus for interconnecting multiple programmable logic devices. In a preferred embodiment of the invention, an interconnect chip couples one programmable logic device to another...
6487651 MIMD arrangement of SIMD machines  
An SIMD array processor having a scalable and flexible architecture. The SIMD array architecture includes an array of processing elements, a plurality of processor controllers, and at least one...
6460146 System and method for establishing processor redundancy  
The present invention relates to providing processor redundancy in a system such as a router. According to an embodiment of the present invention, in a system having two or more processors,...
6453409 Digital signal processing system  
A digital signal processing system has a control processor, a signal processor, and a plurality of memories. A signal processor carries out signal processing under control of the control processor....
6453344 Multiprocessor servers with controlled numbered of CPUs  
A multiprocessor system having a total number of available CPUs partitioned into one or more smaller pools of CPUs called servers where the number of CPUs available to a server is reduced below the...
6424870 Parallel processor  
A parallel processor system has a plurality of nodes interconnected by a network for communication under control of a network interface controller of each node. The network interface controller...
6404439 SIMD control parallel processor with simplified configuration  
According to the SIMD control parallel processing method for performing common operation in parallel in a plurality of elements, comprising first retaining means for retaining operation data...
6366998 Reconfigurable functional units for implementing a hybrid VLIW-SIMD programming model  
The present invention generally relates to a hybrid VLIW-SIMD programming model for a digital signal processor. The hybrid programming model broadcasts a packet of information to a plurality of...
6353898 Resource management in a clustered computer system  
Methods, systems, and devices are provided for managing resources in a computing cluster. The managed resources include cluster nodes themselves, as well as sharable resources such as memory...
6351799 Integrated circuit for executing software programs  
The integrated circuit executes software programs. The electronic components of the integrated circuit and/or the electrical connections between them can be selectively broken and/or created. The...
6330657 Pairing of micro instructions in the instruction queue  
An apparatus and method are presented for increasing the throughput within a single-channel of a pipeline microprocessor. Back-to-back pairs of micro instructions are evaluated to determine if they...
6311241 Method and configuration for transferring programs  
A method for transferring programs to an electronic unit, in which the program to be transferred is stored on a plug-in device. The program is transferred to the electronic unit after the plug-in...
6308252 Processor method and apparatus for performing single operand operation and multiple parallel operand operation  
A processor includes n-bit (e.g., 128-bit) register circuitry for holding instruction operands. Instruction decode circuitry decodes processor instructions from an instruction stream. Arithmetic...
6298409 System for data and interrupt posting for computer devices  
A system for monitoring issuance of interrupt and transaction commands without involving central processor units of computer systems. The system employs a fabric controller to manage transaction...
6275890 Low latency data path in a cross-bar switch providing dynamically prioritized bus arbitration  
The present invention provides a cross-bar switch which includes a plurality of master bus ports, the master bus ports adapted to receive a plurality of master buses; a plurality of slave bus...
6275845 Collective communication apparatus in multiprocessor system  
A collective communication apparatus in a multiprocessor system which shortens communication processing time by reducing data transfer that utilizes communication paths of low performance includes...
6272616 Method and apparatus for executing multiple instruction streams in a digital processor with multiple data paths  
A parallel processing architecture for a digital processor capable of alternately operating in a single threaded mode, a SIMD (single instruction, multiple data) mode and a MIMD (multiple...
6260088 Single integrated circuit embodying a risc processor and a digital signal processor  
A single integrated circuit includes first and second data processors operating on different instruction sets independently operating on disjoint programs and data. The single integrated circuit...
6249826 System and method for media status notification  
After it is determined that a memory storage device supports media status notification (MSN), the operating system (OS) enables MSN by sending a command to the device that disables the ejection...
6223175 Method and apparatus for high-speed approximate sub-string searches  
A technique for searching in a source sequence for a target sequence using parallel processing. Each symbol of the target sequence to a corresponding processing element, where the processing...
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