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8180998 System of lanes of processing units receiving instructions via shared memory units for data-parallel or task-parallel operations  
A system for performing data-parallel operations and task-parallel operations. A first switch fabric node (SFN) includes first and second lane processing engines (LPEs). The first LPE includes a...
8112613 Selecting broadcast SIMD instruction or cached MIMD instruction stored in local memory of one of plurality of processing elements for all elements in each unit  
Disclosed is a mixed mode parallel processor system in which N number of processing elements PEs, capable of performing SIMD operation, are grouped into M (=N÷S) processing units PUs performing ...
8103854 Methods and apparatus for independent processor node operations in a SIMD array processor  
A control processor is used for fetching and distributing single instruction multiple data (SIMD) instructions to a plurality of processing elements (PEs). One of the SIMD instructions is a thread...
8074224 Managing state information for a multi-threaded processor  
Embodiments of the present invention facilitate dynamically adapting to state information changes in a graphics processing environment. In one embodiment, a master register holds state information...
8027962 Techniques for asynchronous command interface for scalable and active data warehousing  
Techniques for asynchronous command processing within a parallel processing environment are provided. A command is raised or received within a parallel processing data warehousing environment. A...
8020168 Dynamic virtual software pipelining on a network on chip  
A NOC for dynamic virtual software pipelining including IP blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through a memory...
7979674 Re-executing launcher program upon termination of launched programs in MIMD mode booted SIMD partitions  
Executing MIMD programs on a SIMD machine, the SIMD machine including a plurality of compute nodes, each compute node capable of executing only a single thread of execution, the compute nodes...
7962906 Compiler method for employing multiple autonomous synergistic processors to simultaneously operate on longer vectors of data  
A compiler includes a mechanism for employing multiple synergistic processors to execute long vectors. The compiler receives a single source program. The compiler identifies vectorizable loop code...
7945433 Hardware simulation accelerator design and method that exploits a parallel structure of user models to support a larger user model size  
A system and method for design verification and, more particularly, a hardware simulation accelerator design and method that exploits a parallel structure of user models to support a large user...
7916864 Graphics processing unit used for cryptographic processing  
A graphics processing unit is programmed to carry out cryptographic processing so that fast, effective cryptographic processing solutions can be provided without incurring additional hardware...
7890735 Multi-threading processors, integrated circuit devices, systems, and processes of operation and manufacture  
A multi-threaded microprocessor (1105) for processing instructions in threads. The microprocessor (1105) includes first and second decode pipelines (1730.0, 1730.1), first and second execute...
7882312 State engine for data processor  
A state engine receives multiple requests from a parallel processor for a shared state. The state engine includes at least one state element and the at least one state element is adapted to...
7853775 Processing elements grouped in MIMD sets each operating in SIMD mode by controlling memory portion as instruction cache and GPR portion as tag  
Disclosed is a mixed mode parallel processor system in which N number of processing elements PEs, capable of performing SIMD operation, are grouped into M (=N÷S) processing units PUs performing ...
7831804 Multidimensional processor architecture  
A processor architecture includes a number of processing elements for treating input signals. The architecture is organized according to a matrix including rows and columns, the columns of which...
7831802 Executing Multiple Instructions Multiple Data (‘MIMD’) programs on a Single Instruction Multiple Data (‘SIMD’) machine  
Executing Multiple Instructions Multiple Data (‘MIMD’) programs on a Single Instruction Multiple Data (‘SIMD’) machine, the SIMD machine including a plurality of compute nodes, each compute node ca...
7831803 Executing multiple instructions multiple date (‘MIMD’) programs on a single instruction multiple data (‘SIMD’) machine  
Executing MIMD programs on a SIMD machine, including establishing on the SIMD machine a plurality of SIMD partitions; booting a first SIMD partition in MIMD mode; executing, on a compute node of...
7818541 Data processing architectures  
A data processing architecture comprising: an input device for receiving an incoming stream of data packets; anda plurality of processing elements which are operable to process data received...
7818539 System and method for performing efficient conditional vector operations for data parallel architectures involving both input and conditional vector values  
A processor implements conditional vector operations in which, for example, an input vector containing multiple operands to be used in conditional operations is divided into two or more output...
7814295 Moving processing operations from one MIMD booted SIMD partition to another to enlarge a SIMD partition  
Executing MIMD programs on a SIMD machine, including establishing SIMD partitions on the SIMD machine; booting SIMD partitions in MIMD mode; executing MIMD programs on the compute nodes of a first...
7814296 Arithmetic units responsive to common control signal to generate signals to selectors for selecting instructions from among respective program memories for SIMD / MIMD processing control  
Provided is a data processing circuit. A control unit outputs an operation control signal and a memory control signal. A plurality of program memories each outputs a command in response to the...
7814462 Methods and apparatus for parallel execution of a process  
In one embodiment, a process may be performed in parallel on a parallel server by defining a data type that may be used to reference data stored on the parallel server and overloading a...
7809925 Processing unit incorporating vectorizable execution unit  
A vectorizable execution unit is capable of being operated in a plurality of modes, with the processing lanes in the vectorizable execution unit grouped into different combinations of logical...
7778396 Telephone status notification system  
A telephone line status notification system including at least one telephone line having a status, a communications network, at least one communications terminal which is connectable to the...
7779180 Semiconductor device and system for performing data processing  
A data processing module includes: a data converter having a TranslateData interface for receiving input data and sending output data, a Property interface for sending and receiving parameter data...
7752419 Method and system for managing hardware resources to implement system functions using an adaptive computing architecture  
The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The exemplary IC embodiment includes a plurality of...
7730463 Efficient generation of SIMD code in presence of multi-threading and other false sharing conditions and in machines having memory protection support  
A computer implemented method, system and computer program product for automatically generating SIMD code. The method begins by analyzing data to be accessed by a targeted loop including at least...
7730280 Methods and apparatus for independent processor node operations in a SIMD array processor  
A control processor is used for fetching and distributing single instruction multiple data (SIMD) instructions to a plurality of processing elements (PEs). One of the SIMD instructions is a thread...
7657784 Self-reparable semiconductor and method thereof  
A self-reparable semiconductor comprises M functional units each including N sub-functional units. Corresponding ones of the N sub-functional units in each of the M functional units perform the...
7640155 Extensible memory architecture and communication protocol for supporting multiple devices in low-bandwidth, asynchronous applications  
A target interface system for interfacing selected components of a communication system and methods for manufacturing and using same. The target interface system includes target interface logic...
7634637 Execution of parallel groups of threads with per-instruction serialization  
In a processor, a SIMD group (a group of threads for which instructions are issued in parallel using single instruction, multiple data instruction issue techniques) is logically divided into two or...
7515899 Distributed grid computing method utilizing processing cycles of mobile phones  
Additional computing power is captured using the idle processing power of mobile phones incorporated into a grid computing system, wherein the system is capable of pushing projects out to available...
7487302 Service layer architecture for memory access system and method  
A memory subsystem includes a memory controller operable to generate first control signals according to a standard interface. A memory interface adapter is coupled to the memory controller and is...
7467286 Executing partial-width packed data instructions  
A method and apparatus are provided for executing packed data instructions. According to one aspect of the invention, a processor includes registers, a register renaming unit coupled to the...
7457938 Staggered execution stack for vector processing  
In one embodiment, the present invention includes a method for executing an operation on low order portions of first and second source operands using a first execution stack of a processor and...
7441098 Conditional execution of instructions in a computer  
A method of executing instructions in a computer system on operands containing a plurality of packed objects in respective lanes of the operand is described. Each instruction defines an operation...
7418575 Long instruction word processing with instruction extensions  
A system for adding reconfigurable computational instructions to a computer, the system comprising a processor operable to execute a set of instructions of a computer program comprising a set of...
7404066 Active memory command engine and method  
A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array...
7401333 Array of parallel programmable processing engines and deterministic method of operating the same  
The present invention provides an array of parallel programmable processing engines interconnected by a switching network. At least some of the processing engines execute a thread, and at least...
7392329 System and method for applying an action initiated for a portion of a plurality of devices to all of the plurality of devices  
In accordance with one embodiment of the present invention, a method of applying an action initiated for a portion of a plurality of devices to all of the plurality of devices is provided. The...
7383427 Multi-scalar extension for SIMD instruction set processors  
A method is provided for executing a plurality of parallel executable sequences of instructions on a processor having a plurality of execution units operated by a single instruction unit. The...
7360005 Software programmable multiple function integrated circuit module  
An electrically programmable multiple selectable function integrated circuit module has a plurality of optionally selectable function circuits, which receive and manipulate a plurality of input...
7313646 Interfacing of functional modules in an on-chip system  
An electronic system comprises an initiator module and a target module addressable by the initiator module, and an interface and control module for interfacing between respective communication...
7035991 Surface computer and computing method using the same  
A surface computer includes an address generator for generating an address for adjusting surface region data concerning at least a storage region and a concurrent computer, provided at a subsequent...
7028107 Process for automatic dynamic reloading of data flow processors (DFPS) and units with two- or three- dimensional programmable cell architectures (FPGAS, DPGAS, and the like)  
A system for communication between a plurality of functional elements in a cell arrangement and a higher-level unit is described. The system may include, for example, a configuration memory...
6944744 Apparatus and method for independently schedulable functional units with issue lock mechanism in a processor  
A functional unit of a processor may be configured to operate on instructions as either a single, wide functional unit or as multiple, independent narrower units. For example, an execution unit may...
6928535 Data input/output configuration for transfer among processing elements of different processors  
An image input section and a signal processing section are provided. The image input section includes an array of pixel in which a plurality of pixels having a CMOS type photoelectric converting...
6925548 Data processor assigning the same operation code to multiple operations  
A data processor can assign a greater number of operations to instruction codes with shorter length, thereby implementing high performance, high code efficiency and low cost data processor. The...
6848041 Methods and apparatus for scalable instruction set architecture with dynamic compact instructions  
A hierarchical instruction set architecture (ISA) provides pluggable instruction set capability and support of array processors. The term pluggable is from the programmer's viewpoint and relates to...
6839828 SIMD datapath coupled to scalar/vector/address/conditional data register file with selective subpath scalar processing mode  
There is provided a processor designed to operate in a plurality of modes for processing vector and scalar instructions. Register files are each for storing scalar and vector data and address...
6785800 Single instruction stream multiple data stream processor  
A SIMD processor includes plural processor elements (PEs) each having a processing unit for data processing, a register for holding data to be processed or already processed by the processing unit,...
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