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7619541 Remote sensor processing system and method  
A sensor assembly includes a sensor operable to sense a physical parameter and generate an electrical signal responsive to the sensed physical parameter. Local processing circuitry is physically...
7617403 Method and apparatus for controlling heat generation in a multi-core processor  
The disclosed methodology and apparatus may reduce heat generation in a multi-core processor. In one embodiment, a multi-core processor cycles selected processor cores off in a predetermined...
7603492 Automatic generation of streaming data interface circuit  
A streaming data interface device ( 700 ) of a streaming processing system ( 200 ) is automatically generated by selecting a set of circuit parameters ( 610 ) consistent with a set of circuit...
7600104 Method and system for parallel vector data processing of vector data having a number of data elements including a defined first bit-length  
System and method are provided for parallel vector data processing having a data processor capable of vector data having a defined first bit-length. In one embodiment, at least one of first and...
7587711 System and method for generalized imaging or computing tasks utilizing a language agent and one or more specifications  
The present invention discloses a method and system for specifying and executing computing tasks in a preboot execution environment in general, and, in particular, a method and system for...
7581084 Method and apparatus for efficient loading and storing of vectors  
A method and apparatus for loading and storing vectors from and to memory, including embedding a location identifier in bits comprising a vector load and store instruction, wherein the location...
7548248 Method and apparatus for image blending  
Methods and apparatuses for blending two images using vector table look up operations. In one aspect of the invention, a method to blend two images includes: loading a vector of keys into a vector...
7543119 Vector processor  
A vector processing system provides high performance vector processing using a System-On-a-Chip (SOC) implementation technique. One or more scalar processors (or cores) operate in conjunction with...
7526629 Vector processing apparatus with overtaking function to change instruction execution order  
A vector processing apparatus includes a main memory, an instruction issuing section which issues instructions, an overtaking control circuit which outputs the instructions received from the...
7526456 Method of operation for parallel LCP solver  
A method of operating a Linear Complementarity Problem (LCP) solver is disclosed, where the LCP solver is characterized by multiple execution units operating in parallel to implement a competent...
7503049 Information processing apparatus operable to switch operating systems  
An information processing apparatus switches between an Operating System 1 and an Operating System 2 during operation and comprises: a storing unit including a first area storing data managed...
7487302 Service layer architecture for memory access system and method  
A memory subsystem includes a memory controller operable to generate first control signals according to a standard interface. A memory interface adapter is coupled to the memory controller and is...
7467286 Executing partial-width packed data instructions  
A method and apparatus are provided for executing packed data instructions. According to one aspect of the invention, a processor includes registers, a register renaming unit coupled to the...
7466316 Apparatus, system, and method for distributing work to integrated heterogeneous processors  
An integrated circuit includes at least two different types of processors, such as a graphics processor and a video processor. At least one operation is commonly by supported by two different types...
7457938 Staggered execution stack for vector processing  
In one embodiment, the present invention includes a method for executing an operation on low order portions of first and second source operands using a first execution stack of a processor and...
7447873 Multithreaded SIMD parallel processor with loading of groups of threads  
In a multithreaded processing core, groups of threads are executed using single instruction, multiple data (SIMD) parallelism by a set of parallel processing engines. Input data defining objects to...
7446773 Apparatus, system, and method for integrated heterogeneous processors with integrated scheduler  
An integrated circuit includes at least two different types of processors. The integrated circuit includes an integrated host and associated scheduler. At least one operation is supported by two or...
7418574 Configuring a portion of a pipeline accelerator to generate pipeline date without a program instruction  
A peer-vector machine includes a host processor and a hardwired pipeline accelerator. The host processor executes a program, and, in response to the program, generates host data, and the pipeline...
7404065 Flow optimization and prediction for VSSE memory operations  
In one embodiment, a method for flow optimization and prediction for vector streaming single instruction, multiple data (SIMD) extension (VSSE) memory operations is disclosed. The method comprises...
7356710 Security message authentication control instruction  
A method, system and computer program product for computing a message authentication code for data in storage of a computing environment. An instruction specifies a unit of storage for which an...
7275147 Method and apparatus for data alignment and parsing in SIMD computer architecture  
Execution of a single stand-alone instruction manipulates two n bit strings of data to pack data or align the data. Decoding of the single instruction identifies two registers of n bits each and a...
7257695 Register file regions for a processing system  
According to some embodiments, a dynamic region in a register file may be described for an operand. The described region may, for example, store multiple data elements, each data element being...
7206857 Method and apparatus for a network processor having an architecture that supports burst writes and/or reads  
A method is described that involves recognizing that an input queue state has reached a buffer's worth of information. The method also involves generating a first request to read a buffer's worth...
7197625 Alignment and ordering of vector elements for single instruction multiple data processing  
The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a...
7197623 Multiple processor cellular radio  
Protocol processor intended to be associated with at least one main processor of a system with a view to the execution of tasks to which the main processor is not suited. The Protocol Processor...
7197606 Information storing method for computer system including a plurality of computers and storage system  
A computer 10 a stores boot information OA 1 and application information AP 1 stored on a local disk 16 a , the information being respectively stored as an OS 1 shared file group in a shared...
7159099 Streaming vector processor with reconfigurable interconnection switch  
A re-configurable, streaming vector processor ( 100 ) is provided which includes a number of function units ( 102 ), each having one or more inputs for receiving data values and an output for...
7149877 Byte execution unit for carrying out byte instructions in a processor  
A disclosed byte execution unit receives byte instruction information and two operands, and performs an operation specified by the byte instruction information upon one or both of the operands,...
7146486 SIMD processor with scalar arithmetic logic units  
A scalar processor that includes a plurality of scalar arithmetic logic units and a special function unit. Each scalar unit performs, in a different time interval, the same operation on a different...
7043627 SIMD operation system capable of designating plural registers via one register designating field  
In view of a necessity of alleviating factors obstructing an effect of SIMD operation such as in-register data alignment in high speed formation of an SIMD processor, numerous data can be supplied...
7043607 Information processing system and cache flash control method used for the same  
The vector unit 21 outputs a first flash address to the flash address array 24 . The vector unit 31 outputs a second flash address to the flash address array 34 . In the master unit 2 , the...
6996698 Blocking processing restrictions based on addresses  
Processing restrictions of a computing environment are filtered and blocked, in certain circumstances, such that processing continues despite the restrictions. One restriction includes an...
6968445 Multithreaded processor with efficient processing for convergence device applications  
A multithreaded processor includes an instruction decoder for decoding retrieved instructions to determine an instruction type for each of the retrieved instructions, an integer unit coupled to the...
6968402 System and method for storing chunks of first cache line and second cache line in a buffer in a first and second chunk order  
Techniques to buffer and present chunks are disclosed. In some embodiments, a first interface may receive chunks of a first cache line, and a second interface may receive chunks of a second cache...
6963341 Fast and flexible scan conversion and matrix transpose in a SIMD processor  
The present invention provides efficient ways to implement scan conversion and matrix transpose operations using vector multiplex operations in a SIMD processor. The present method provides a very...
6950834 Online database table reorganization  
A database table reorganization is defined to permit online access of the table during the reorganization. Records are reorganized in the database table by vacating records from a defined number of...
6924802 Efficient function interpolation using SIMD vector permute functionality  
A system, method, and computer program product are provided for generating display data. The data processing system loads coefficient values corresponding to a behavior of a selected function in...
6807620 Game system with graphics processor  
The present invention relates to the architecture and use of a computer system optimized for the efficient modeling of graphics. The computer system has a primary processor and a graphics...
6782470 Operand queues for streaming data: A processor register file extension  
The register file of a processor includes embedded operand queues. The configuration of the register file into registers and operand queues is defined dynamically by a computer program. The...
6734874 Graphics processing unit with transform module capable of handling scalars and vectors  
A method, apparatus and article of manufacture are provided for handling both scalar and vector components during graphics processing. To accomplish this, vertex data is received in the form of...
6697930 Multistandard video decoder and decompression method for processing encoded bit streams according to respective different standards  
A pipeline video decoder and decompression system handles a plurality of separately encoded bit streams arranged as a single serial bit stream of digital bits and having separately encoded pairs of...
6675379 Automatic removal of array memory leaks  
A method for memory management in execution of a program by a computer having a memory includes identifying in the program an array of array elements. At a given point in the program, a range of...
6624819 Method and system for providing a flexible and efficient processor for use in a graphics processing system  
A method and system for processing graphics data in a computer system are disclosed. The method and system including providing a general-purpose processor and providing a vector co-processor...
6542981 Microcode upgrade and special function support by executing RISC instruction to invoke resident microcode  
A method and apparatus for invoking microcode instructions resident on a processor by executing a special RISC instruction on the processor such that special functions are provided. In one...
6523026 Method for retrieving semantically distant analogies  
A process of identifying terms or sets of terms in target domains having functional relationships (roles) analogous to terms (contained in the query) selected from a source domain whereby...
6448983 Method for selection of a design of experiment  
A method for assisting a user in selecting a design of experiment. The method includes obtaining a plurality of attributes associated with a plurality of experimental designs. A series of questions...
6349347 Method and system for shortening boot-up time based on absence or presence of devices in a computer system  
A method of configuring peer devices without the unnecessary delay in boot up time using a compatibility bridge. Upon initiating a configuration cycle, a BIOS initialization scans all peer devices...
6343337 Wide shifting in the vector permute unit  
A crossbar is implemented within multimedia facilities of a processor to perform vector permute operations, in which the bytes of a source operand are reordered in the target output. The crossbar...
6324600 System for controlling movement of data in virtual environment using queued direct input/output device and utilizing finite state machine in main memory with two disjoint sets of states representing host and adapter states  
A method and an apparatus for controlling movement of data between any host and any network including a set of devices in a computing system environment having a main memory with a queuing...
6317819 Digital signal processor containing scalar processor and a plurality of vector processors operating from a single instruction  
A digital data processor integrated circuit (1) includes a plurality of functionally identical first processor elements (6A) and a second processor element (5). The first processor elements are...
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