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8952727 Hum generation circuitry  
Systems and methods for clock generation and distribution are disclosed. Embodiments include arrangements of synchronization signals implemented using a mesh circuit. The mesh circuit is comprised...
8904148 Processor architecture with switch matrices for transferring data along buses  
There is described a processor architecture, comprising: a plurality of first bus pairs, each first bus pair including a respective first bus running in a first direction (for example, left to...
8843928 Method and apparatus for a general-purpose, multiple-core system for implementing stream-based computations  
A method and system of efficient use and programming of a multi-processing core device. The system includes a programming construct that is based on stream-domain code. A programmable core based...
8688956 Execution engine for executing single assignment programs with affine dependencies  
The execution engine is a new organization for a digital data processing apparatus for highly parallel execution of structured fine-grain parallel computations. The execution engine includes a...
8638805 Packet draining from a scheduling hierarchy in a traffic manager of a network processor  
Described embodiments provide for restructuring a scheduling hierarchy of a network processor having a plurality of processing modules and a shared memory. The scheduling hierarchy schedules...
8190855 Coupling data for interrupt processing in a parallel processing environment  
An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the...
8145881 Data processing device and method  
A data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other...
8108653 Processor architectures for enhanced computational capability and low latency  
A processor includes a compute array comprising a first plurality of compute engines serially connected along a data flow path such that data flows between successive compute engines at successive...
8094768 Multi-channel timing recovery system  
The present invention discloses a novel multi-channel timing recovery scheme that utilizes a shared CORDIC to accurately compute the phase for each tone. Then a hardware-based linear combiner...
8055881 Computing nodes for executing groups of instructions  
A computation node according to various embodiments of the invention includes at least one input port capable of being coupled to at least one first other 5 computation node, a first store coupled...
7996652 Processor architecture with switch matrices for transferring data along buses  
A processor architecture includes a plurality of elements arranged in an array of rows and columns and a plurality of first and second bus pairs with the first pair being located between different...
7844796 Data processing device and method  
A data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other...
7831810 Communicating signals between semiconductor chips using round-robin-coupled micropipelines  
Embodiments of the present invention provide a system for transferring data between a receiver chip and a transmitter chip. The system includes a set of data path circuits in the transmitter chip...
7747771 Register access protocol in a multihreaded multi-core processor  
A method and mechanism for managing access to a plurality of registers in a processing device are contemplated. A processing device includes multiple nodes coupled to a ring bus, each of which...
7743235 Processor having a dedicated hash unit integrated within  
A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support...
7680962 Stream processor and information processing apparatus  
An array type processor comprises a data path unit to execute processing, and a state management unit to control the state of the data path unit in accordance with a command that specifies...
7653805 Processing in pipelined computing units with data line and circuit configuration rule signal line  
A semiconductor device for performing data processing by performing a plurality of computations in cycles includes a pipeline formed by connecting a plurality of computing units in series, each of...
7653804 Resource sharing in multiple parallel pipelines  
A signal processing network and method for generating code for such a signal processing network are described. Pipeline blocks are each coupled to receive control signaling and associated...
7650484 Array—type computer processor with reduced instruction storage  
An array-type computer processor including a data path unit communicating with a state control unit obtains data of a predetermined number of cooperative partial instruction codes, and operates...
7644255 Method and apparatus for enable/disable control of SIMD processor slices  
Methods and apparatus provide for disabling at least some data path processing circuits of a SIMD processing pipeline, in which the processing circuits are organized into a matrix of slices and...
7636835 Coupling data in a parallel processing environment  
An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the...
7624248 Managing memory in a parallel processing environment  
An integrated circuit comprises a plurality of tiles. Each tile comprises: a processor, a switch including switching circuitry to forward data received over data paths from other tiles to the...
7577820 Managing data in a parallel processing environment  
An integrated circuit comprises a plurality of tiles. Each tile comprises a processor including a storage module, wherein the processor is configured to process multiple streams of instructions, a...
7574582 Processor array including delay elements associated with primary bus nodes  
There is disclosed a processor array, which achieves an approximately constant latency. Communications to and from the farthest array elements are suitably pipelined for the distance, while...
7555630 Method and apparatus to provide efficient communication between multi-threaded processing elements in a processor unit  
A context forwarding bus efficiently communicates control and data between processing elements in a processor unit having a plurality of processing elements. Control and data information is...
7539845 Coupling integrated circuits in a parallel processing environment  
An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the...
7500239 Packet processing system  
According to some embodiments, each of a plurality of threads receives a start signal from a previous thread and a data packet from a buffer. Each thread issues a command to store the data packet...
7483429 Method and system for flexible network processor scheduler and data flow  
A network processor dataflow chip and method for flexible dataflow are provided. The dataflow chip comprises a plurality of on-chip data transmission and scheduling circuit structures. The data...
7461236 Transferring data in a parallel processing environment  
An integrated circuit includes a plurality of tiles. Each tile comprises a processor; and a switch including switching circuitry to forward data over data paths from other tiles to the processor...
7444495 Processor and programmable logic computing arrangement  
A computing arrangement including a processor and programmable logic. In various embodiments, the arrangement includes an instruction processing circuit coupled to a programmable logic circuit,...
7426628 Run-time node prefetch prediction in dataflow graphs  
A method for run-time prediction of a next caller of a shared functional unit, wherein the shared functional unit is operable to be called by two or more callers out of a plurality of callers. The...
7404066 Active memory command engine and method  
A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array...
7370123 Information processing apparatus  
A descriptor queue composed of descriptors containing input address information that represents an address for storing data to be processed and output address information that represents an...
7305649 Automatic generation of a streaming processor circuit  
A streaming processor circuit of a processing system is automatically generated by selecting a set of circuit parameters consistent with a set of circuit constraints and generating a...
7290123 System, device and method of maintaining in an array loop iteration data related to branch entries of a loop detector  
A loop detector with an array to store a counter of loop iterations, where the number of entries in the array may be, for example, smaller than the number of entries in the loop detector. Entries...
7287146 Array-type computer processor  
An array-type computer processor stops, with a plurality of computer programs held, a state control unit and a data-path unit, upon input of event data for task switching. The array-type computer...
7260558 Simultaneously searching for a plurality of patterns definable by complex expressions, and efficiently generating data for such searching  
An apparatus, a carrier medium carrying computer readable code to implement a method, and a method for searching for a plurality of patterns definable by complex expressions, and further, for...
7130986 Determining if a register is ready to exchange data with a processing element  
According to some embodiments, it is determined if a register is ready to exchange data with a processing element.
7100020 Digital communications processor  
An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313,...
7000090 Center focused single instruction multiple data (SIMD) array system  
A center focussed SIMD array system including an SIMD array including a plurality of processing elements arranged in a number of columns and rows and having two mutually perpendicular axes of...
7000022 Flow of streaming data through multiple processing modules  
Frame-based streaming data flows through a graph of multiple interconnected processing modules. The modules have a set of performance parameters whose values specify the sensitivity of each module...
6993764 Buffered coscheduling for parallel programming and enhanced fault tolerance  
A computer implemented method schedules processor jobs on a network of parallel machine processors or distributed system processors. Control information communications generated by each process...
6993639 Processing instruction addressed by received remote instruction and generating remote instruction to respective output port for another cell  
Embodiments of the invention relate to a processing cell for use in computing systems. Generally, a processing cell generates remote instructions to be received and processed by at least one other...
6976150 Resource flow computing device  
A scalable processing system includes a memory device having a plurality of executable program instructions, wherein each of the executable program instructions includes a timetag data field...
6967950 Pull transfers and transfer receipt confirmation in a datapipe routing bridge  
In a network of digital signal processor nodes connected in a peer-to-peer relationship, a data packet sent to a node causes a return transmission from that node. The requester digital signal...
6948048 Method and apparatus for interleaved exchange in a network mesh  
A method for exchanging information within a mesh network that has an array of nodes defined by four quadrants. The method includes the initial step of exchanging information from a set of nodes...
6920562 Tightly coupled software protocol decode with hardware data encryption  
An encryption mechanism tightly-couples hardware data encryption functions with software-based protocol decode processing within a pipelined processor of a programmable processing engine....
6904512 Data flow processor  
A data flow processor includes a number of hardware units each having more than one mode. A plurality of hardware units may be connected together to implement a flow made up of a series of...
6874079 Adaptive computing engine with dataflow graph based sequencing in reconfigurable mini-matrices of composite functional blocks  
Aspects of a method and system for digital signal processing within an adaptive computing engine are described. These aspects include a mini-matrix, the mini-matrix comprising a set of composite...
6859869 Data processing system  
A data processing system, wherein a data flow processor (DFP) integrated circuit chip is provided which comprises a plurality of orthogonally arranged homogeneously structured cells, each cell...

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