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7603541 |
Array synchronization with counters
A method is disclosed for achieving synchronization in an array of semi-synchronous devices. A processor array has an array of processor elements, wherein each of said processor elements comprises...
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7596678 |
Method of shifting data along diagonals in a group of processing elements to transpose the data
A transpose of data appearing in a plurality of processing elements comprises shifting the data along diagonals of the plurality of processing elements until the processing elements in the diagonal...
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7581079 |
Processor composed of memory nodes that execute memory access instructions and cooperate with execution nodes to execute function instructions
A shared memory network for communicating between processors using store and load instructions is described. A new processor architecture which may be used with the shared memory network is also...
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7577821 |
IC containing matrices of plural type operation units with configurable routing wiring group and plural delay operation units bridging two wiring groups
An integrated circuit device comprising a data processing block including a first matrix and a second matrix is disclosed. The first matrix and the second matrix respectively include a plurality of...
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7577820 |
Managing data in a parallel processing environment
An integrated circuit comprises a plurality of tiles. Each tile comprises a processor including a storage module, wherein the processor is configured to process multiple streams of instructions, a...
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7574582 |
Processor array including delay elements associated with primary bus nodes
There is disclosed a processor array, which achieves an approximately constant latency. Communications to and from the farthest array elements are suitably pipelined for the distance, while...
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7574581 |
Cross-chip communication mechanism in distributed node topology to access free-running scan registers in clock-controlled components
A method of communicating between processing units on different integrated circuit chips in a multi-processor computer system by issuing a command from a source processing unit to a destination...
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7571300 |
Modular distributive arithmetic logic unit
A memory system includes a plurality of memory blocks, each having a dedicated local arithmetic logic unit (ALU). A data value having a plurality of bytes is stored such that each of the bytes is...
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7565287 |
Methods and apparatus for efficient vocoder implementations
Techniques for implementing vocoders in parallel digital signal processors are described. A preferred approach is implemented in conjunction with the BOPS® Manifold Array (ManArray™) processing...
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RE40741 |
System and method for synchronization of video display outputs from multiple PC graphics subsystems
A system and method for synchronization of video raster display outputs from multiple PC graphics subsystems to facilitate synchronized output onto multiple displays are disclosed. The system and...
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7536493 |
Method and apparatus for identifying a service processor with current setting information
The aspects of the present invention provide a computer implemented method, an apparatus, and a computer usable program code for identifying a service processor with current setting information....
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7529917 |
Method and apparatus for interrupt handling during loop processing in reconfigurable coarse grained array
A processor including a coarse grained array including a plurality of function units and a plurality of register files, wherein a loop to be executed by the coarse grained array is split into a...
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7515899 |
Distributed grid computing method utilizing processing cycles of mobile phones
Additional computing power is captured using the idle processing power of mobile phones incorporated into a grid computing system, wherein the system is capable of pushing projects out to available...
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7509442 |
Informational-signal-processing apparatus, functional block, and method of controlling the functional block
An informational-signal-processing apparatus has a plurality of functional blocks and a control block that controls operations of the functional blocks. Each of the functional blocks performs a...
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7506297 |
Methodology for scheduling, partitioning and mapping computational tasks onto scalable, high performance, hybrid FPGA networks
An automatically reconfigurable high performance FPGA system that includes a hybrid FPGA network and an automated scheduling, partitioning and mapping software tool adapted to configure the hybrid...
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7506134 |
Hardware resource based mapping of cooperative thread arrays (CTA) to result matrix tiles for efficient matrix multiplication in computing system comprising plurality of multiprocessors
The present invention enables efficient matrix multiplication operations on parallel processing devices. One embodiment is a method for mapping CTAs to result matrix tiles for matrix multiplication...
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7493475 |
Instruction vector-mode processing in multi-lane processor by multiplex switch replicating instruction in one lane to select others along with updated operand address
An improved superscalar processor. The processor includes multiple lanes, allowing multiple instructions in a bundle to be executed in parallel. In vector mode, the parallel lanes may be used to...
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7480785 |
Parallel processing device and parallel processing method
A row decoding circuit ( 171 ) outputs a select signal to a row set in a row range setting unit ( 172 ) to select a select signal line ( 103 ), processing results from processing circuits ( 102 )...
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7472392 |
Method for load balancing an n-dimensional array of parallel processing elements
One aspect of the present invention relates to a method for balancing the load of an n-dimensional array of processing elements (PEs), wherein each dimension of the array includes the processing...
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7461234 |
Loosely-biased heterogeneous reconfigurable arrays
A heterogeneous array includes clusters of processing elements. The clusters include a combination of ALUs and multiplexers linked by direct connections and various general-purpose routing...
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7457939 |
Processing system with dedicated local memories and busy identification
A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and...
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7454593 |
Row and column enable signal activation of processing array elements with interconnection logic to simulate bus effect
The present invention relates to the control of an array of processing elements in a parallel processor using row and column select lines. For each column in the array, a column select line...
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7451293 |
Array of Boolean logic controlled processing elements with concurrent I/O processing and instruction sequencing
A computer processor having an integrated instruction sequencer, array of processing engines, and I/O controller. The instruction sequencer sequences instructions from a host, and transfers these...
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7451292 |
Methods for transmitting data across quantum interfaces and quantum gates using same
Quantum gaps exist between an origin and a destination that heretofore have prevented reliably utilizing the advantages of quantum computing. To predict the outcome of instructions with precision,...
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7447872 |
Inter-chip processor control plane communication
An inter-chip communication (ICC) mechanism enables any processor in a pipelined arrayed processing engine to communicate directly with any other processor of the engine over a low-latency...
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7441100 |
Processor synchronization in a multi-processor computer system
A method for synchronizing a plurality of processors of a multi-processor computer system on a synchronization point is disclosed. The method includes triggering a first set of processors, using a...
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7426448 |
Method and apparatus for diagnosing broken scan chain based on leakage light emission
A mechanism for diagnosing broken scan chains based on leakage light emission is provided. An image capture mechanism detects light emission from leakage current in complementary metal oxide...
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7418541 |
Method for indirect access to a support interface for memory-mapped resources to reduce system connectivity from out-of-band support processor
A method and apparatus are provided for a support interface for memory-mapped resources. A support processor sends a sequence of commands over and FSI interface to a memory-mapped support interface...
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7401333 |
Array of parallel programmable processing engines and deterministic method of operating the same
The present invention provides an array of parallel programmable processing engines interconnected by a switching network. At least some of the processing engines execute a thread, and at least...
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7392350 |
Method to operate cache-inhibited memory mapped commands to access registers
In a multiprocessor environment, by executing cache-inhibited reads or writes to registers, a scan communication is used to rapidly access registers inside and outside a chip originating the...
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7356819 |
Task distribution
Methods, signals, devices and systems are provided for matching tasks with processing units. A region within a multi-faceted task space is allocated to a processing unit. A point in the...
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7315933 |
Re-configurable circuit and configuration switching method
The present invention is a re-configurable circuit capable of reducing latency by selecting a route for skipping the FF of an operation unit and outputting data to a connection destination...
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7266255 |
Distributed multi-sample convolution
A multi-chip system is disclosed for distributing the convolution process. Rather than having multiple convolution chips working in parallel with each chip working on a different portion of the...
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7176914 |
System and method for directing the flow of data and instructions into at least one functional unit
A system and method are provided for directing the flow of data and instructions into at least one functional unit. In one embodiment of a system of components defining a plurality of nodes, a...
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7155466 |
Policy-based management of a redundant array of independent nodes
An archive cluster application runs in a distributed manner across a redundant array of independent nodes. Each node preferably runs a complete archive cluster application instance. A given nodes...
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7130934 |
Methods and apparatus for providing data transfer control
A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing...
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7100020 |
Digital communications processor
An integrated circuit ( 203 ) for use in processing streams of data generally and streams of packets in particular. The integrated circuit ( 203 ) includes a number of packet processors ( 307, 313,...
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7069557 |
Network processor which defines virtual paths without using logical path descriptors
A virtual path feature in which several virtual channels share an assigned amount of bandwidth is implemented in a network processor. The network processor maintains a schedule indicative of...
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7069416 |
Method for forming a single instruction multiple data massively parallel processor system on a chip
A single chip active memory includes a plurality of memory stripes, each coupled to a full word interface and one of a plurality of processing element (PE) sub-arrays. The large number of couplings...
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7043562 |
Irregular network
Irregularities are provided in at least one dimension of a torus or mesh network for lower average path length and lower maximum channel load while increasing tolerance for omitted end-around...
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7028107 |
Process for automatic dynamic reloading of data flow processors (DFPS) and units with two- or three- dimensional programmable cell architectures (FPGAS, DPGAS, and the like)
A system for communication between a plurality of functional elements in a cell arrangement and a higher-level unit is described. The system may include, for example, a configuration memory...
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7020761 |
Blocking processing restrictions based on page indices
Processing restrictions of a computing environment are filtered and blocked, in certain circumstances, such that processing continues despite the restrictions. One restriction includes an...
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6996504 |
Fully scalable computer architecture
A scalable computer architecture capable of performing fully scalable simulations includes a plurality of processing elements (PEs) and a plurality of interconnections between the PEs. In this...
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6993764 |
Buffered coscheduling for parallel programming and enhanced fault tolerance
A computer implemented method schedules processor jobs on a network of parallel machine processors or distributed system processors. Control information communications generated by each process...
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6990566 |
Multi-channel bi-directional bus network with direction sideband bit for multiple context processing elements
A method and an apparatus for configuration of multiple context processing elements (MCPEs) are described. The method and an apparatus is capable of selectively transmitting data over a...
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6968442 |
Parallel computer with improved access to adjacent processor and memory elements
A parallel computer of this invention includes a plurality of memory elements and a plurality of processing elements and each of the processing elements is connected to logically adjacent memory...
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6967950 |
Pull transfers and transfer receipt confirmation in a datapipe routing bridge
In a network of digital signal processor nodes connected in a peer-to-peer relationship, a data packet sent to a node causes a return transmission from that node. The requester digital signal...
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6928539 |
Multiprocessor application interface requiring no ultilization of a multiprocessor operating system
A test monitor loaded into a multiprocessor machine comprises a program ( 31 ) designed to interpret a script language for writing tests, a program ( 29 ) that constitutes a kernel part for...
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6915388 |
Method and system for efficient use of a multi-dimensional sharing vector in a computer system
A multiprocessor computer system includes a plurality of processor nodes, a memory, and an interconnect network connecting the plurality of processor nodes to the memory. The memory includes a...
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6883084 |
Reconfigurable data path processor
A reconfigurable data path processor comprises a plurality of independent processing elements. Each of the processing elements advantageously comprising an identical architecture. Each processing...
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