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9015448 Message broadcast with router bypassing  
A processor and method for broadcasting data among a plurality of processing cores is disclosed. The processor includes a plurality of processing cores connected by point-to-point connections. A...
9009444 System and method for LUN control management  
A method, computer program product, and computing system for receiving a reservation for a LUN from Host A, wherein the LUN is defined within a data array. A lock for the LUN is defined as Host A....
9003274 Scheduling start-up and shut-down of mainframe applications using topographical relationships  
The illustrative embodiments provide for a system and recordable type medium for representing actions in a data processing system. A table is generated. The table comprises a plurality of rows and...
8935510 System structuring method in multiprocessor system and switching execution environment by separating from or rejoining the primary execution environment  
For flexibly setting up an execution environment according to contents of processing to be executed while taking stability or a security level into consideration, the multiple processor system...
8934332 Multi-threaded packet processing  
A system is disclosed for concurrently processing order sensitive data packets. A first data packet from a plurality of sequentially ordered data packets is directed to a first offload engine. A...
8904152 Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architecture  
Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with...
8892850 Endpoint-based parallel data processing with non-blocking collective instructions in a parallel active messaging interface of a parallel computer  
Methods, apparatuses, and computer program products for endpoint-based parallel data processing with non-blocking collective instructions in a parallel active messaging interface (‘PAMI’) of a...
8886916 Endpoint-based parallel data processing with non-blocking collective instructions in a parallel active messaging interface of a parallel computer  
Endpoint-based parallel data processing with non-blocking collective instructions in a PAMI of a parallel computer is disclosed. The PAMI is composed of data communications endpoints, each...
8880809 Memory controller with inter-core interference detection  
Embodiments are described for a method for controlling access to memory in a processor-based system comprising monitoring a number of interference events, such as bank contentions, bus...
8874878 Thread synchronization in a multi-thread, multi-flow network communications processor architecture  
Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate...
8830829 Parallel processing using multi-core processor  
Disclosed are methods, systems, paradigms and structures for processing data packets in a communication network by a multi-core network processor. The network processor includes a plurality of...
8832413 Processing system with interspersed processors and communication elements having improved wormhole routing  
A processing system includes processors and dynamically configurable communication elements (DCCs) coupled together in an interspersed arrangement. A source device may transfer a data item through...
8825924 Asynchronous computer communication  
A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner...
8769244 SIMD parallel computer system, SIMD parallel computing method, and control program  
Uniforming of the processing load is efficiently realized. Each processing element configuring an SIMD parallel computer system includes a data storage module that stores data processed or...
8761188 Multi-threaded software-programmable framework for high-performance scalable and modular datapath designs  
In the provided architecture, one or more multi-threaded processors may be combined with hardware blocks. The resulting combination allows for data packets to undergo a processing sequence having...
8751772 Methods and apparatus for scalable array processor interrupt detection and response  
Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution...
8683182 System and apparatus for group floating-point inflate and deflate operations  
Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and...
8665727 Placement and routing for a multiplexer-based interconnection network  
A computer-implemented method is described for determining cost in a non-blocking routing network that provides routing functionality using a single level of a plurality of multiplexers in each...
8656141 Architecture and programming in a parallel processing environment with switch-interconnected processors  
An integrated circuit includes a plurality of tiles. Each tile includes a pipelined processor configured to process multiple streams of instructions for the processor; and a switch including...
8638805 Packet draining from a scheduling hierarchy in a traffic manager of a network processor  
Described embodiments provide for restructuring a scheduling hierarchy of a network processor having a plurality of processing modules and a shared memory. The scheduling hierarchy schedules...
8625422 Parallel processing using multi-core processor  
Disclosed are methods, systems, paradigms and structures for processing data packets in a communication network by a multi-core network processor. The network processor includes a plurality of...
8607029 Dynamic reconfigurable circuit with a plurality of processing elements, data network, configuration memory, and immediate value network  
A dynamic reconfigurable circuit including a plurality of processing elements each provided with an arithmetic data input port, a configuration data input port and an output port, a data network...
8572353 Condensed router headers with low latency output port calculation  
Communicating among cores in a computing system comprising a plurality of cores, each core comprising a processor and a switch, includes: routing a packet from an origin core to a destination core...
8549259 Performing a vector collective operation on a parallel computer having a plurality of compute nodes  
Systems, methods and articles of manufacture are disclosed for performing a vector collective operation on a parallel computing system that includes multiple compute nodes and a network connecting...
8549258 Configurable processing apparatus and system thereof  
A configurable processing apparatus includes a plurality of processing units, at least an instruction synchronization control circuit, and at least a configuration memory. Each processing...
8532288 Selectively isolating processor elements into subsets of processor elements  
A cryptographic engine for modulo N multiplication, which is structured as a plurality of almost identical, serially connected Processing Elements, is controlled so as to accept input in blocks...
8489857 Processor cluster architecture and associated parallel processing methods  
A parallel processing architecture comprising a cluster of embedded processors that share a common code distribution bus. Pages or blocks of code are concurrently loaded into respective program...
8489858 Methods and apparatus for scalable array processor interrupt detection and response  
Hardware and software techniques for interrupt detection and response are provided in a scalable pipelined array processor environment. Utilizing these techniques, a sequential program execution...
8484276 Processing array data on SIMD multi-core processor architectures  
Techniques are disclosed for converting data into a format tailored for efficient multidimensional fast Fourier transforms (FFTS) on single instruction, multiple data (SIMD) multi-core processor...
8468323 Clockless computer using a pulse generator that is triggered by an event other than a read or write instruction in place of a clock  
A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner...
8464025 Signal processing apparatus with signal control units and processor units operating based on different threads  
A signal processing apparatus able to raise a processing capability in processing accompanying access to a storing means is provided. Stream control units (SCU) 203—0 to 203—3 access data at an...
8417733 Dynamic atomic bitsets  
Embodiments of the present invention provide techniques, including systems, methods, and computer readable medium, for dynamic atomic bitsets. A dynamic atomic bitset is a data structure that...
8370605 Computer architecture for a mobile communication platform  
A system includes first and second processors, first and second graphics processing units (GPUs), one or more peripheral devices, a switch matrix, and processor-readable memory. The switch matrix...
8327114 Matrix processor proxy systems and methods  
In some embodiments, processor-to-processor and/or broadcast proxies are designated in a microprocessor matrix comprising a plurality of mesh-interconnected matrix processors when default...
8312053 Dynamic atomic arrays  
Embodiments of the present invention provide techniques, including systems, methods, and computer readable medium, for dynamic atomic arrays. A dynamic atomic array is a data structure that...
8276116 Algebra operation method, apparatus, and storage medium thereof  
An algebra operation method includes the steps of converting algebra operations for a plurality of objects which appear in a program into an algebra operation sequence object described using...
8200948 Apparatus and method for performing re-arrangement operations on data  
An apparatus and method are provided for performing re-arrangement operations on data. The data processing apparatus has a register data store with a plurality of registers for storing data, and...
8195921 Method and apparatus for decoding multithreaded instructions of a microprocessor  
A microprocessor capable of decoding a plurality of instructions associated with a plurality of threads is disclosed. The microprocessor may comprise a first array comprising a first plurality of...
8185719 Message routing scheme for an array having a switch with address comparing component and message routing component  
Each possessor node in an array of nodes has a respective local node address, and each local node address comprises a plurality of components having an order of addressing significance from most...
8161267 Methods and apparatus for scalable array processor interrupt detection and response  
Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution...
8151090 Sequentially propagating instructions of thread through serially coupled PEs for concurrent processing respective thread on different data and synchronizing upon branch  
A systolic data processing apparatus includes a processing element (PE) array and control unit. The PE array comprises a plurality of PEs, each PE executing a thread with respect to different data...
8151089 Array-type processor having plural processor elements controlled by a state control unit  
A multiplicity of processor elements that are arranged in rows and columns individually execute data processing in accordance with instruction codes that are individually set as data and supply...
8145880 Matrix processor data switch routing systems and methods  
According to some embodiments, an integrated circuit comprises a microprocessor matrix of mesh-interconnected matrix processors. Each processor comprises a data switch including a data switch link...
8135229 Image processing method and device  
An image processing method and device for processing multiple rows of pixels of an image simultaneously with a single instruction. The processing includes selecting a pixel window having a...
8131975 Matrix processor initialization systems and methods  
In some embodiments, an integrated circuit comprises a microprocessor matrix including a plurality of mesh-interconnected matrix processors, wherein each matrix processor comprises a data switch...
8112612 Processing system with interspersed processors using selective data transfer through communication elements  
A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one...
8108661 Data processing apparatus and method of controlling the data processing apparatus  
Provided are a data processing apparatus and a method of controlling the data processing apparatus. The data processing apparatus may select a single stream processor from a plurality of stream...
8103855 Linking functional blocks for sequential operation by DONE and GO components of respective blocks pointing to same memory location to store completion indicator read as start indicator  
The present disclosure provides a methodology for reducing congestion of a processing unit, preferably by configuring a plurality of functional blocks to run in parallel or in series without the...
8090913 Coherency groups of serially coupled processing cores propagating coherency information containing write packet to memory  
A system has a first plurality of cores in a first coherency group. Each core transfers data in packets. The cores are directly coupled serially to form a serial path. The data packets are...
8086824 Stream processing system having a reconfigurable memory module  
A stream processing system includes a stream processing module coupled to a memory module and operable so as to fetch stream elements from the memory module, to process the stream elements fetched...
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