Matches 101 - 150 out of 181 < 1 2 3 4 >
Match Document Document Title
6085303 Seralized race-free virtual barrier network  
Improved method and apparatus for facilitating barrier and eureka synchronization in a massively parallel processing system. The present barrier/eureka synchronization mechanism provides a...
6085304 Interface for processing element array  
A memory-like I/O system is provided for interfacing a processing element array with a host system. The I/O system includes cornerturn logic for converting data written to the processing element...
6079008 Multiple thread multiple data predictive coded parallel processing system and method  
A parallel processing system or processor has a computing architecture including a plurality of execution units to repeatedly distribute instruction streams within the processor via corresponding...
6067609 Pattern generation and shift plane operations for a mesh connected computer  
An apparatus for processing data has a Single-Instruction-Multiple-Data (SIMD) architecture, and a number of features that improve performance and programmability. The apparatus includes a...
6038688 Node disjoint path forming method for hypercube having damaged node  
A node disjoint path forming method for a hypercube having a damaged node which is capable of using unused nodes (surplus nodes) in an n-number of node disjoint paths each having a length of n with...
6035374 Method of executing coded instructions in a multiprocessor having shared execution resources including active, nap, and sleep states in accordance with cache miss latency  
A method of executing coded instructions in a dynamically configurable multiprocessor having shared execution resources including steps of placing a first processor in an active state upon booting...
6021453 Microprocessor unit for use in an indefinitely extensible chain of processors with self-propagation of code and data from the host end, self-determination of chain length and ID, (and with multiple orthogonal channels and coordination ports)  
A novel architecture is based on a general purpose microcomputer with an "upstream" bus and a "downstream" bus. The upstream bus interfaces to an integrated multiport RAM that is shared between an...
5991866 Method and system for generating a program to facilitate rearrangement of address bits among addresses in a massively parallel processor system  
A system and method for generating a program to enable reassignment of data items among processors in a massively-parallel computer to effect a predetermined rearrangement of address bits. The...
5991867 Transmit scheduler for an asynchronous transfer mode network and method of operation  
A transmit scheduler and method of operation are provided for an asynchronous transfer mode network. The transmit scheduler is operable to write data to and read data from a scheduler table and a...
5978580 Passing arrays to stored procedures  
A method, apparatus, and article of manufacture for passing a VisualBasic array argument to an SQL stored procedure executed by a computer. The VisualBasic array is first created in the memory of...
5956519 Picture end token in a system comprising a plurality of pipeline stages  
A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over...
5944811 Superscalar processor with parallel issue and execution device having forward map of operand and instruction dependencies  
In a superscalar processor for fetching a prescribed peak number of instructions in parallel in each period until such instructions are fetched to a predetermined peak number, such as ten, an...
5943502 Apparatus and method for fast 1D DCT  
A method and apparatus is disclosed for a fast, one-dimensional, discrete cosine transform (1D DCT) of eight samples, and for a fast, one-dimensional, inverse discrete cosine transform (1D IDCT)...
5935230 Multiprocessor arrangement including bus arbitration scheme involving plural CPU clusters that address each other as "phantom" CPUs  
At least two clusters of CPUs are present in a multiprocessor computer system. Each CPU cluster has a given number of CPUs, each CPU having an associated ID such as an ID number. An additional ID...
5923891 System for minimizing disk access using the computer maximum seek time between two furthest apart addresses to control the wait period of the processing element  
A method and apparatus for minimizing the cumulative seek time required to complete a plurality of sequential disk accesses within a parallel processing computer system. The method and apparatus...
5915123 Method and apparatus for controlling configuration memory contexts of processing elements in a network of multiple context processing elements  
A method and apparatus for providing local control of processing elements in a network of multiple context processing element are provided. A multiple context processing element is configured to...
5901324 Parallel processor system for transmitting data in small buffers  
In a parallel processor system, each processor is connected to a secondary memory. A main memory of a sender processor has first small buffers and a main memory of a receiver processor has second...
5898881 Parallel computer system with error status signal and data-driven processor  
A parallel computer system includes a plurality of processing elements each comprising a network control unit. The network control unit of the processing element has ports to north, east, west and...
5892890 Computer system with parallel processor for pixel arithmetic  
A pixel processor, for use in conjunction with a color video monitor or an all points addressable color print engine, includes brush logic, mask logic, clip logic, and a multi-pixel logic unit to...
5892962 FPGA-based processor  
A multiprocessor having an input/output controller, a process controller, and a multidimensional arrays of field programmable gate arrays (FPGAs), each FPGA having its own local memory. The...
5889424 Pulse width modulation operation circuit  
The invention provides a pulse width modulation operation circuit for processing an m-bit pulse width modulation signal which is represented by a number n of sub pulse width modulation signals,...
5850268 Parallel processor apparatus  
To provide a parallel processor apparatus which can perform processing with a good efficiency on signals comprised of data of different lengths. A parallel processor configured by a serial...
5842035 Parallel computer utilizing less memory by having first and second memory areas  
A parallel computer comprising a plurality of processor elements and a network interconnecting the same, wherein each of the plurality of processor elements includes: a memory unit including a...
5838985 Parallel processor with memory/ALU inhibiting feature  
A parallel processor comprises a data input register, a plurality of processor elements, a data output register, control means and instruction signal generating means. The data input register is...
5826095 Method and apparatus for maintaining the order of data items processed by parallel processors  
A data processing system includes two or more parallel processors, a distributor and a combiner. The processors process input data items and generate corresponding output data items. The...
5822606 DSP having a plurality of like processors controlled in parallel by an instruction word, and a control processor also controlled by the instruction word  
The Parallel DSP Chip has a general purpose, reduced instruction set for parallel digital signal processing. The following pertains to the preferred embodiment. Most instruction words are 32 bits...
5822608 Associative parallel processing system  
Multiprocessor parallel computing systems and a byte serial SIMD processor parallel architecture is used for parallel array processing with a simplified architecture adaptable to chip...
5805915 SIMIMD array processing system  
A conventional SIMD processor array architecture's functions are amplified by a SIMIMD architecture where more programmable flexibility would be useful. Decision making in general and specifically...
5802385 Array processing system with each processor including router and which selectively delays input/output of individual processors in response delay instructions  
In one aspect, the invention provides parallel processing apparatus comprising an array of data processors 4. arranged to operate synchronously, and a plurality of data buses. Each data processor 4...
5790879 Pipelined-systolic single-instruction stream multiple-data stream (SIMD) array processing with broadcasting control, and method of operating same  
A pipelined-systolic SIMD array processing architecture includes an array of processing elements, registers-delays, and multiplexers. One or more of the registers-delays having one or more...
5765012 Controller for a SIMD/MIMD array having an instruction sequencer utilizing a canned routine library  
A controller for a SIMD processor array that can execute instructions within each processing element is described. This three stage hierarchical controller executes instructions at the function,...
5765009 Barrier synchronization system in parallel data processing  
A data parallel processing system is equipped with two or more processing elements. On termination of data processing, each processing element informs an interconnection device of it. The...
5752068 Mesh parallel computer architecture apparatus and associated methods  
A Monolithic Synchronous Processor (MeshSP) processes data and incorporates a mesh parallel computer architecture, primarily SIMD, thereby combining high data throughput with modest size, weight,...
5752067 Fully scalable parallel processing system having asynchronous SIMD processing  
Parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a...
5732211 Advanced data server having a plurality of rings connected to a server controller which controls the rings to cause them to receive and store data and/or retrieve and read out data  
An advanced data server including an I/O ring coupled to at least one I/O access channel which provides data to the I/O ring or reads data out from the I/O ring; a disc array ring coupled to least...
5708839 Method and apparatus for providing bus protocol simulation  
A method and apparatus for providing bus protocol simulation in a multi-processor data processing system (10). A plurality of edge interface circuits (14,16) are used to interface a first bus (32,...
5682544 Massively parallel diagonal-fold tree array processor  
A massively parallel processor apparatus having an instruction set architecture for each of the N 2 the PEs of the structure. The apparatus which we prefer will have a PE structure consisting of...
5682491 Selective processing and routing of results among processors controlled by decoding instructions using mask value derived from instruction tag and processor identifier  
An array processor topology reconfiguration system and method enables processor elements in an array to dynamically reconfigure their mutual interconnection for the exchange of arithmetic results...
5680550 Digital computer for determining a combined tag value from tag values selectively incremented and decremented reflecting the number of messages transmitted and not received  
A digital computer includes a plurality of processing elements, a command processor, a diagnostic processor and a communications network. The processing elements each performs data processing and...
5666169 Parallel processor apparatus having means for processing signals of different lengths  
To provide a parallel processor apparatus which can perform processing with a good efficiency on signals comprised of data of different lengths. A parallel processor configured by a serial...
5632041 Sequence information signal processor for local and global string comparisons  
A sequence information signal processing integrated circuit chip designed to perform high speed calculation of a dynamic programming algorithm based upon the algorithm defined by Waterman and...
5630129 Dynamic load balancing of applications  
An application-level method for dynamically maintaining global load balance on a parallel computer, particularly on massively parallel MIMD computers. Global load balancing is achieved by...
5600822 Resource allocation synchronization in a parallel processing system  
A method and system for synchronizing allocation of resources in a parallel processing system. At predefined time intervals, each user application executing in a parallel processing system is given...
5588152 Advanced parallel processor including advanced support hardware  
A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a...
5586289 Method and apparatus for accessing local storage within a parallel processing computer  
A processor within a parallel processing computer having a plurality of processors, where each processor is directly connected to a local storage memory. Each processor contains a principal...
5581777 Parallel processor memory transfer system using parallel transfers between processors and staging registers and sequential transfers between staging registers and memory  
A massively parallel processor is provided with a plurality of clusters. Each cluster includes a plurality of processor elements ("PEs") and a cluster memory. Each PE of the cluster has associated...
5581778 Advanced massively parallel computer using a field of the instruction to selectively enable the profiling counter to increase its value in response to the system clock  
A parallel computing system comprising N blocks of processors, where N is an integer greater than 1. Each block of the N blocks of processors contains M processors, where M is an integer greater...
5579527 Apparatus for alternately activating a multiplier and a match unit  
A processor for use in a parallel computing system. The processor contains: a memory for storing operand values; an arithmetic logic unit (ALU) for performing arithmetic logic operations on operand...
5560030 Transfer processor with transparency  
Data processor with a transparency detection data transfer controller. Transparency register stores transparency data. Source address controller calculates source addresses for recall of data to be...
5555430 Interrupt control architecture for symmetrical multiprocessing system  
A symmetrical multiprocessing system is provided that includes centralized interrupt control unit. The interrupt control unit is coupled to a plurality of processing units and to a plurality of...
Matches 101 - 150 out of 181 < 1 2 3 4 >