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7620678 Method and system for reducing the time-to-market concerns for embedded system design  
Aspects for reducing the time-to-market concerns for embedded system design are described. The aspects include providing an infrastructure to support a plurality of heterogeneous processing nodes...
7613899 Reconfigurable data processing device and method  
A reconfigurable data processing device equipped with a plurality of data processing units controls timing of switching contents of data processing executed by each of the plurality of data...
7603540 Using field programmable gate array (FPGA) technology with a microprocessor for reconfigurable, instruction level hardware acceleration  
A method for dynamically programming Field Programmable Gate Arrays (FPGAs) in a coprocessor, the coprocessor coupled to a processor, includes: beginning an execution of an application by the...
7599489 Accelerating cryptographic hash computations  
Provided is an apparatus and method for accelerating cryptographic hash computations. For example, in a cryptographic hash computation such as SHA-1, multiple execution units in a processor can...
7590821 Digital signal processing integrated circuit with I/O connections  
A digital signal processing integrated circuit contains an array of interconnected and programmed or programmable digital signal processors ( 10 ). Configurable multiplexing circuits ( 12 ), are...
7587613 Method and apparatus for selectively enabling a microprocessor-based system  
A system for selectively enabling a microprocessor-based system is disclosed. State information that describes the operating conditions or circumstances under which a user intends to operate the...
7577821 IC containing matrices of plural type operation units with configurable routing wiring group and plural delay operation units bridging two wiring groups  
An integrated circuit device comprising a data processing block including a first matrix and a second matrix is disclosed. The first matrix and the second matrix respectively include a plurality of...
7577820 Managing data in a parallel processing environment  
An integrated circuit comprises a plurality of tiles. Each tile comprises a processor including a storage module, wherein the processor is configured to process multiple streams of instructions, a...
7577727 Dynamic multiple cluster system reconfiguration  
According to the present invention, methods and apparatus are provided to allow dynamic multiple cluster system configuration changes. In one example, processors in the multiple cluster system...
7571303 Reconfigurable integrated circuit  
A reconfigurable integrated circuit is provided wherein the available hardware resources can be optimised for a particular application. Dynamically reconfiguring (in both real-time and non...
7568084 Semiconductor integrated circuit including multiple basic cells formed in arrays  
A basic cell capable of a fixed operating frequency regardless of the configuration information, which is also capable of effectively utilizing the arithmetic logic circuit within the cell in a LSI...
7565525 Runtime configurable arithmetic and logic cell  
A cascadable arithmetic and logic unit (ALU) which is configurable in function and interconnection. No decoding of commands is needed during execution of the algorithm. The ALU can be reconfigured...
7543283 Flexible instruction processor systems and methods  
The present invention relates to the design-time and run-time environments of instruction processors implemented in re-programmable hardware. In one aspect the present invention provides a design...
7529917 Method and apparatus for interrupt handling during loop processing in reconfigurable coarse grained array  
A processor including a coarse grained array including a plurality of function units and a plurality of register files, wherein a loop to be executed by the coarse grained array is split into a...
7512873 Parallel processing apparatus dynamically switching over circuit configuration  
A parallel processing apparatus dynamically switching over a circuit configuration includes a plurality of computing elements, a network establishing connections between the plural computing...
7509479 Reconfigurable global cellular automaton with RAM blocks coupled to input and output feedback crossbar switches receiving clock counter value from sequence control unit  
The invention relates to a computer containing a RAM-based primary part (Ht) with a stucturable RAM unit ( 2 ). On the input side, a first crossbar switch ( 1 ) is located upstream of said unit and...
7493468 Method for broadcasting instructions/data to a plurality of processors in a multiprocessor device via aliasing  
A method for broadcasting instructions/data to a plurality of processors in a multiprocessor device via aliasing is provided. In order to broadcast data to a plurality of processors, a control...
7489779 Hardware implementation of the secure hash standard  
An integrated circuit for implementing the secure hash algorithm is provided. According to one aspect of the integrated circuit, the integrated circuit includes a data path and a controller...
7487302 Service layer architecture for memory access system and method  
A memory subsystem includes a memory controller operable to generate first control signals according to a standard interface. A memory interface adapter is coupled to the memory controller and is...
7484086 Data processing apparatus, and method of reconfiguring reconfigurable processing circuit  
Information relating to heat-release value of a processing circuit or amount of input data applied to the processing circuit is detected and the processing circuit is reconfigured in accordance...
7464251 Method and apparatus for configuring arbitrary sized data paths comprising multiple context processing elements  
A method and an apparatus for configuring arbitrary sized data paths comprising multiple context processing elements (MCPEs) are provided. Multiple MCPEs may be chained to form wider-word data...
7461236 Transferring data in a parallel processing environment  
An integrated circuit includes a plurality of tiles. Each tile comprises a processor; and a switch including switching circuitry to forward data over data paths from other tiles to the processor...
7461234 Loosely-biased heterogeneous reconfigurable arrays  
A heterogeneous array includes clusters of processing elements. The clusters include a combination of ALUs and multiplexers linked by direct connections and various general-purpose routing...
7418579 Component with a dynamically reconfigurable architecture  
The invention relates to a component with a large grain dynamically reconfigurable architecture for processing of data by processing units organized in rows and connected to each other through...
7418575 Long instruction word processing with instruction extensions  
A system for adding reconfigurable computational instructions to a computer, the system comprising a processor operable to execute a set of instructions of a computer program comprising a set of...
7418574 Configuring a portion of a pipeline accelerator to generate pipeline date without a program instruction  
A peer-vector machine includes a host processor and a hardwired pipeline accelerator. The host processor executes a program, and, in response to the program, generates host data, and the pipeline...
7415594 Processing system with interspersed stall propagating processors and communication elements  
A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one...
7398380 Dynamic hardware partitioning of symmetric multiprocessing systems  
Dynamic hardware partitioning of symmetric multiprocessing systems enables on-the-fly provisioning of servers of varying performance characteristics by configuring physical partitions having...
7386704 Pipeline accelerator including pipeline circuits in communication via a bus, and related system and method  
A pipeline accelerator includes a bus and a plurality of pipeline units, each unit coupled to the bus and including at least one respective hardwired-pipeline circuit. By including a plurality of...
7383424 Computer architecture containing processor and decoupled coprocessor  
A computer system comprises a first processor 1 and a second processor 2 for use as a coprocessor to the first processor 1 . The system has a main memory 3 . The system also has a decoupling...
7380100 Data processing system and control method utilizing a plurality of date transfer means  
The present invention provides a data processing system that includes a plurality of processing units and first, second, and third data transfer means. The first data transfer means connects a...
7379418 Method for ensuring system serialization (quiesce) in a multi-processor environment  
A method of ensuring system serialization in a multiprocessor multi-nodal environment is used to force all processors in a multiprocessor environment to temporarily suspend operations while one...
7376811 Method and apparatus for performing computations and operations on data using data steering  
A data processing system architecture is based upon a hardware engine that includes a plurality of functional units and data routing units that interconnect the functional units. The hardware...
7350054 Processor having array of processing elements whose individual operations and mutual connections are variable  
An arrayed processor has a plurality of processing elements each having a plurality of types of arithmetic logic units for processing data having different numbers of bits from one another. The...
7340585 Method and system for fast linked processor in a system on a chip (SoC)  
A fast linked multiprocessor network ( 22 ) including a plurality of processing modules ( 24, 26, 28, 30, 32 , and 34 ) implemented on a field programmable gate array ( 10 ) and a plurality of...
7325123 Hierarchical interconnect for configuring separate interconnects for each group of fixed and diverse computational elements  
An integrated circuit having computational elements. As least one of the computational elements has a fixed architecture. An interconnection network is coupled to a first group of the computational...
7320064 Reconfigurable computing architecture for space applications  
A reconfigurable computer includes a reconfigurable processing element configured to process raw payload data in accordance with a configuration that is applied to the reconfigurable processing...
7320062 Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements  
The present invention concerns configuration of a new category of integrated circuitry for adaptive computing. The various embodiments provide an executable information module for an adaptive...
7318143 Reuseable configuration data  
An information processor for executing a program comprising a plurality of separate program instructions is provided. The processor comprises processing logic operable to individually execute said...
7305638 Method and system for ROM coding to improve yield  
A method for improving yield of a process for fabricating a read-only memory (ROM) includes evaluating a yield of a ROM fabrication process associated with a first ROM design. At least two...
7266672 Method and apparatus for retiming in a network of multiple context processing elements  
A method and an apparatus for retiming in a network of multiple context processing elements in a network of multiple context processing elements are provided. A programmable delay element is...
7237088 Methods and apparatus for providing context switching between software tasks with reconfigurable control  
The ManArray core indirect VLIW processor consists of an array controller sequence processor (SP) merged with a processing element (PE0) closely coupling the SP with the PE array and providing the...
7237087 Reconfigurable multidimensional array processor allowing runtime reconfiguration of selected individual array cells  
An expanded arithmetic and logic unit (EALU) with special extra functions is integrated into a configurable unit for performing data processing operations. The EALU is configured by a function...
7237086 Configuring a management module through a graphical user interface for use in a computer system  
A customization program for use in customizing a baseboard management controller used for monitoring operation of various computer system components is disclosed. A user interacts with the...
7225320 Control architecture for a high-throughput multi-processor channel decoding system  
A multi-processor unit includes a first domain for processing data according to first configuration information and having multiple first domain processors each connected to communication apparatus...
7210129 Method for translating programs for reconfigurable architectures  
A method for translating high-level languages to reconfigurable architectures is disclosed. The method includes building a finite automaton for calculation. The method further includes forming a...
7191312 Configurable interconnection of multiple different type functional units array including delay type for different instruction processing  
An integrated circuit device with a data processing block is provided, the data processing block including a plurality of operation units that are arranged in a matrix, a plurality of first wire...
7188192 Controlling multiple context processing elements based on transmitted message containing configuration data, address mask, and destination indentification  
A method and apparatus for providing local control of processing elements in a network of multiple context processing elements (MCPEs). A MCPE stores configuration memory contexts and maintains...
7185226 Fault tolerance in a supercomputer through dynamic repartitioning  
A multiprocessor, parallel computer is made tolerant to hardware failures by providing extra groups of redundant standby processors and by designing the system so that these extra groups of...
7174443 Run-time reconfiguration method for programmable units  
A method of run-time reconfiguration of a programmable unit is provided, the programmable unit including a plurality of reconfigurable function cells in a multidimensional arrangement. An event is...
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