Matches 151 - 200 out of 208 < 1 2 3 4 5 >
Match Document Document Title
5784702 System and method for dynamically performing resource reconfiguration in a logically partitioned data processing system  
A dynamic reconfiguration request for a change in a system's physical configuration is transmitted from a configuration controller to a hypervisor controlling operating systems executing in one or...
5778244 Digital signal processing unit using digital signal processor array with recirculation  
A digital signal processing unit with an array of digital signal processors (DSP) is provided with a recirculation path for data sequences which cannot be fully processed by a single pass through...
5774642 Architecture for dynamic service processor exchange providing multitasking environment where multiple processors have access to a system configuration table  
A computer system for dynamic service processor exchange comprising a first, active service processor connected by a network and a maintenance unit (CMU) to a central system (4) and to a second,...
5768561 Tokens-based adaptive video processing arrangement  
A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over...
5765188 Memory presence and type detection using multiplexed memory select line  
A method and apparatus for enabling the detection of memory presence and identification of memory type in a memory system. A memory controller may be connected to a memory bank which may be...
5737623 Multi-processor parallel computer architecture using a parallel machine with topology-based mappings of composite grid applications  
A parallelization process for complex-topology applications is based on an understanding of topology and includes two separate parts: i) an automatic, topology-based data distribution method and...
5729756 Torus networking method and apparatus having a switch for performing an I/O operation with an external device and changing torus size  
A reconfigurable torus network system includes a switch section which is composed of switches for splitting an n-dimensional torus network into subunits or combining the subunits into the torus...
5729754 Associative network method and apparatus  
A reconfigurable, associative network apparatus and method. During a configuration phase of the associative network apparatus, active signals corresponding to wanted input patterns are configured...
5717942 Reset for independent partitions within a computer system  
A method and apparatus for providing a multi-source reset for independent partitions within a multiprocessor computer system. In a system having at least two partitions wherein the at least two...
5715471 Parallel computer  
A parallel computer includes a sequence of adjacent nodes, with each node including at least first and second processing elements and each processing element including a memory. The nodes are...
5710938 Data processing array in which sub-arrays are established and run independently  
A data processing array is partitioned by electronic control signals into multiple sub-arrays which are established and operate independently of each other. In the preferred embodiment, an...
5708836 SIMD/MIMD inter-processor communication  
A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a...
5696986 Computer processor utilizing logarithmic conversion and method of use thereof  
A computer processor for performing mathematical operations includes a logarithm converter which generates log values on a data bus, a plurality of processing elements connected to the data bus, an...
5689661 Reconfigurable torus network having switches between all adjacent processor elements for statically or dynamically splitting the network into a plurality of subsystems  
An n-dimensional torus network-based parallel computer, n being an integer greater than 1, is folded n times with the results of folding embedded in an n-dimensional layer for connection with an...
5680634 Fixed interconnection network method and apparatus for a modular mixed-resolution, N-dimensional configuration control mechanism  
A modular, polymorphic network interconnecting a plurality of electronically reconfigurable devices via a modular, polymorphic interconnect, to permit a fixed, physical configuration of operating...
5649198 Mapping calculation units by dividing a calculation model which can be calculated in parallel on an application program  
This invention aims to perform mapping in a user space without concern for an architecture of a parallel computer and to obtain a high-speed mapping pattern. An N-dimensional model is divided by a...
5649179 Dynamic instruction allocation for a SIMD processor  
A method and apparatus to dynamically allocate instructions to programmable processing element decoders (78, 79, 80) in a SIMD processor (100) includes a source code instruction (71) for the...
5649106 Parallel computer with reconstruction of processor clusters  
A parallel computer having a plurality of cluster buses 2 which are connected to the processor (PE) 1 via the selectors 6. The selectors 6 maintain the same condition until the next instruction is...
5640586 Scalable parallel group partitioned diagonal-fold switching tree computing apparatus  
A parallel computer architecture supporting neural networks utilizing a novel method of separating a triangular array containing N processing elements on each edge into multiple smaller triangular...
5619719 Reduced inter-module circuit path crossovers on circuit boards mounting plural multi-chip modules, through rearranging the north-south-east-west interconnection interfaces of a given module and through selective rotation of each module  
The number of circuit path crossover points on boards mounting plural connected multichip modules is substantially reduced over the number that would otherwise be required. For 4-sided modules and...
5617577 Advanced parallel array processor I/O connection  
A fast I/O for a multi-PME computer system provides a way to break into a network coupling to alternate network couplings. The system coupling is called a zipper. Our I/O zipper concept can be used...
5617575 Interprocessor priority control system for multivector processor  
In a multiprocessor computer system, individual vector processors are provided with priority switching signal control circuits, respectively, and a storage control unit incorporating a priority...
5613146 Reconfigurable SIMD/MIMD processor using switch matrix to allow access to a parameter memory by any of the plurality of processors  
There is disclosed a multiprocessor system and method arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having...
5598570 Efficient data allocation management in multiprocessor computer system  
The present invention comprises a computer system having a plurality of processors configured in an architecture having at least two subgraphs wherein at least a first subgraph and a second...
5594918 Parallel computer system providing multi-ported intelligent memory  
A parallel computer system providing multi-ported intelligent memory is formed of a plurality of nodes or cells interconnected to provide a shared memory with processors of the network and their...
5566341 Image matrix processor for fast multi-dimensional computations  
An apparatus for multi-dimensional computation which comprises a computation engine, including a plurality of processing modules. The processing modules are configured in parallel and compute...
5465375 Multiprocessor system with cascaded modules combining processors through a programmable logic cell array  
In a multiprocessor data processing system, modules are cascaded by means of intermodule buses. Each module comprises a data processing unit, a first memory, a logic cell array programmable into...
5388214 Parallel computer system including request distribution network for distributing processing requests to selected sets of processors in parallel  
A computer comprising a plurality of processing nodes, a control node and a request distribution network. Each processing node receives processing requests and generates in response processed data....
5361367 Highly parallel reconfigurable computer architecture for robotic computation having plural processor cells each having right and left ensembles of plural processors  
In a computer having a large number of single-instruction multiple data (SIMD) processors, each of the SIMD processors has two sets of three individual processor elements controlled by a master...
5347639 Self-parallelizing computer system and method  
A self-parallelizing computer system and method asynchronously processes execution sequences of instructions in two modes of execution on a set of processing elements which communicate with each...
5305462 Mechanism for broadcasting data in a massively parallell array processing system  
An array processing system including a grid array of processing elements, each of which is surrounded by a group of nearest neighbor processing elements in the grid array, each of said processing...
5291611 Modular signal processing unit  
A modular signal processing unit capable of being connected in series, palel or combinations thereof, is provided. Each modular unit is a parallel signal processor that receives input data on a...
5280620 Coupling network for a data processor, including a series connection of a cross-bar switch and an array of silos  
A coupling network for a data processor is described, including, one or more cross bar switches having inputs and outputs and one or more arrays of silos. A series connection is formed in which...
5265207 Parallel computer system including arrangement for transferring messages from a source processor to selected ones of a plurality of destination processors and combining responses  
A parallel computer comprising a plurality of processors and an interconnection network for transferring messages among the processors. At least one of the processors, as a source processor,...
5218709 Special purpose parallel computer architecture for real-time control and simulation in robotic applications  
A Real-time Robotic Controller and Simulator (RRCS) with an MIMD-SIMD parallel architecture for interfacing with an external host computer provides a high degree of parallelism in computation for...
5212773 Wormhole communications arrangement for massively parallel processor  
A parallel processor array is disclosed comprising an array of processor/memories and devices for interconnecting these processor/memories in an n-dimensional pattern having at least 2 n nodes...
5203005 Cell structure for linear array wafer scale integration architecture with capability to open boundary I/O bus without neighbor acknowledgement  
A cell architecture for use in a linear array wafer scale integration includes a plurality of multiplexers, each associated with a boundary of the cell, and each selectively operable to permit...
5168572 System for dynamic selection of globally-determined optimal data path  
A system for choosing a data path through a multi-processor array on a least time and path availability basis. In a preferred embodiment, each processor has an associated path selection element....
5163120 Second nearest-neighbor communication network for synchronous vector processor, systems and methods  
A synchronous vector processor SVP device having a plurality of one-bit processor elements organized in a linear array. The processor elements are all controlled in common by a sequencer, a state...
5151996 Multi-dimensional message transfer router  
A router comprising a plurality of routing nodes interconnected by a plurality of communications links in a multi-dimensional pattern for transferring messages, each message including an address...
5146606 Systems for interconnecting and configuring plurality of memory elements by control of mode signals  
An array processing system including a plurality of processing elements each including a processor and an associated memory module, the system further including a router network over which each...
5031139 Random address system for circuit modules  
The wafer scale integrated circuit comprises an array of undiced chips or modules, each of which includes a data storing or processing circuit, e.g. a dynamic RAM, and configuration logic. Channels...
5020059 Reconfigurable signal processor  
An interconnection scheme among the processing elements ("PEs") of a multiprocessor computing architecture realizes, through PE reconfiguration, both fault tolerance and a wide variety of different...
5014189 Processor array comprising processors connected selectively in series or in parallel  
A processor array has first through N-th processor. Each of first through (N-1)-th switching devices is connected between preceding and succeeding consecutively numbered ones of the first through...
4943909 Computational origami  
A processor architecture that permits the realization of any computing function with a regular array of interconnected procssing elements comprising as few as one processing element. The processing...
4910665 Distributed processing system including reconfigurable elements  
A distributed processing system comprising an array of elements each including a plurality of communication ports on which to send or receive data signals is disclosed. Each element further...
4876644 Parallel pipelined processor  
A processor adapted for parallel and/or pipelined interconnection with other like processors. An arithmetic logic unit has associated with it an output FIFO register stack having output data lines...
4876641 Vlsi data processor containing an array of ICs, each of which is comprised primarily of an array of processing  
A data processor comprises an array of integrated circuits (ICs), each of which comprises an array of data processing elements (PEs) connected to allow transfer of data. The PEs of the data...
4851995 Programmable variable-cycle clock circuit for skew-tolerant array processor architecture  
Using a variable-duration clock circuit, together with programmable duration control to alter the clock waveform within strict rules, permits the programmer to arrange appropriately short durations...
4825359 Data processing system for array computation  
A data processing system for array computation including a global memory, a control processor unit for executing microprograms preloaded from the global memory in a local memory of the processor...
Matches 151 - 200 out of 208 < 1 2 3 4 5 >