Matches 101 - 150 out of 208 < 1 2 3 4 5 >
Match Document Document Title
6480967 Multiple module processing system with reset system independent of reset characteristics of the modules  
A reset module operates in conjunction with a system clock module to provide a combination of reset and clock assertions that can be relied upon to reset conventional processing modules having a...
6477697 ADDING COMPLEX INSTRUCTION EXTENSIONS DEFINED IN A STANDARDIZED LANGUAGE TO A MICROPROCESSOR DESIGN TO PRODUCE A CONFIGURABLE DEFINITION OF A TARGET INSTRUCTION SET, AND HDL DESCRIPTION OF CIRCUITRY NECESSARY TO IMPLEMENT THE INSTRUCTION SET, AND DEVELOPMENT AND VERIFICATION TOOLS FOR THE INSTRUCTION SET  
An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set,...
6470441 Methods and apparatus for manifold array processing  
A manifold array topology includes processing elements, nodes, memories or the like arranged in clusters. Clusters are connected by cluster switch arrangements which advantageously allow changes of...
6467009 Configurable processor system unit  
The configurable processor system includes a processor, an internal system bus, and a programmable logic all interconnected via the internal system bus, on a single integrated circuit.
6457116 Method and apparatus for controlling contexts of multiple context processing elements in a network of multiple context processing elements  
A method and apparatus for providing local control of processing elements in a network of multiple context processing element are provided. A multiple context processing element is configured to...
6449708 Field programmable processor using dedicated arithmetic fixed function processing elements  
A field programmable processor includes a regular array of processing elements, each of which is adapted to perform a fixed arithmetic function on packets of data. The processing elements are...
6401189 General base state assignment for optimal massive parallelism  
General base hypercube transformations using general base perfect shuffles and Kronecker matrix products are applied to the problem of parallel, to massively parallel processing of sparse matrices....
6393504 Dynamic address mapping and redundancy in a modular memory device  
A memory device which utilizes a plurality of memory modules coupled in parallel to a master I/O module through a bus. Each memory module has independent address and command decoders to enable...
6389491 Test instrumentation I/O communication interface and method  
A universal I/O interface is presented which allows communication with a number of different instruments independent of the underlying I/O configuration. The universal I/O interface is a set of...
6349378 Data processing using various data processors  
A data processing arrangement comprises various data processors (P) and a memory arrangement (MA) for supplying input data (Di) to the data processors (P) and for storing output data (Do) from the...
6339807 Multiprocessor system and the bus arbitrating method of the same  
An arbitrator provided to a processor element requests the utilization of a bus sends a bus request signal and a bus request value according to a priority level of the processor element to the bus,...
6298409 System for data and interrupt posting for computer devices  
A system for monitoring issuance of interrupt and transaction commands without involving central processor units of computer systems. The system employs a fabric controller to manage transaction...
6298430 User configurable ultra-scalar multiprocessor and method  
A user-configurable ultra-scalar multiprocessor has a predetermined plurality of distributed configurable signal processors (DCSPs) (1) which are computational clusters that each have at least two...
6282627 Integrated processor and programmable data path chip for reconfigurable computing  
The present invention, generally speaking, provides a reconfigurable computing solution that offers the flexibility of software development and the performance of dedicated hardware solutions. A...
6279098 Method of and apparatus for serial dynamic system partitioning  
A method and apparatus for providing for serially transmitting partitioning information between system partitions, and between system partitions and the corresponding data processing resources....
6279045 Multimedia interface having a multimedia processor and a field programmable gate array  
An integrated circuit architecture for multimedia processing. A single integrated circuit (IC) operates as a system or subsystem, and is adaptable to processing a variety of multimedia algorithms,...
6266760 Intermediate-grain reconfigurable processing device  
A programmable integrated circuit utilizes a large number of intermediate-grain processing elements which are multibit processing units arranged in a configurable mesh. The coarse-grain resources,...
6263415 Backup redundant routing system crossbar switch architecture for multi-processor system interconnection networks  
The present invention provides a new crossbar switch which is implemented by a first plurality of chips. Each chip is completely programmable to couple to every node in the system, e.g., from one...
6240502 Apparatus for dynamically reconfiguring a processor  
A method and apparatus for dynamically reconfiguring a processor involves placing the processor in a first configuration having a first number (m) of strands while the coded instructions comprise...
6226734 Method and apparatus for processor migration from different processor states in a multi-processor computer system  
Multiple instances of operating systems execute cooperatively in a single multiprocessor computer wherein all processors and resources are electrically connected together. The single physical...
6219777 Register file having shared and local data word parts  
Disclosed is a register file used in a multiprocessor composition composed of a plurality of processor elements, the register file having a plurality of words and being provided for each of the...
6219833 Method of using primary and secondary processors  
The compilation of source code to a primary and a secondary processor. The method relates to reconfigurable secondary processors, and is especially relevant to secondary processors which can be...
6199157 System, method and medium for managing information  
A system, method and medium for configuring an item such as a machine having multiple optional components is provided. This is accomplished using "options," which correspond to the optional...
6195738 Combined associative processor and random access memory architecture  
An architecture combining an associative processor memory array and a random access memory is provided. This combination architecture enables utilizing the parallel processing abilities of the...
6167502 Method and apparatus for manifold array processing  
A manifold array topology includes processing elements, nodes, memories or the like arranged in clusters. Clusters are connected by cluster switch arrangements which advantageously allow changes of...
6128720 Distributed processing array with component processors performing customized interpretation of instructions  
A multi-processor array organization is dynamically configured by the inclusion of a configuration topology field in instructions broadcast to the processors in the array. Each of the processors in...
6122747 Intelligent subsystem interface for modular hardware system  
A single chip application specific integrated circuit (ASIC) which provides a flexible, modular interface between a subsystem and a standard system bus. The ASIC includes a...
6122720 Coarse-grained look-up table architecture  
A new programmable logic device architecture with an improved LAB and improved interconnection resources. For interconnecting signals to and from the LABs (200), the global interconnection...
6119226 Memory supporting multiple address protocols  
The present invention provides a new memory device for storage of boot code for microprocessors which boot to either the top or bottom of a memory map on power-up. The device includes a memory...
6112288 Dynamic configurable system of parallel modules comprising chain of chips comprising parallel pipeline chain of processors with master controller feeding command and data  
A programmable, special-purpose, pipeline processing system for processing dynamic programming algorithms. The pipeline processing system includes a plurality of accelerator chips coupled in...
6105102 Mechanism for minimizing overhead usage of a host system by polling for subsequent interrupts after service of a prior interrupt  
An apparatus and method minimizes processing resource of a host system during service of interrupts generated closely in time by at least one peripheral device. The present invention determines,...
6096091 Dynamically reconfigurable logic networks interconnected by fall-through FIFOs for flexible pipeline processing in a system-on-a-chip  
An integrated circuit comprising a plurality of reconfigurable logic networks, one or more buffers, a configuration control network, and an embedded processor, all comprised as an integral part of...
6092174 Dynamically reconfigurable distributed integrated circuit processor and method  
A dynamically reconfigurable distributed integrated circuit processor has at least one two-layer matrix in which a first layer has operative microcomputer modules (1) with local memory (2) grouped...
6067609 Pattern generation and shift plane operations for a mesh connected computer  
An apparatus for processing data has a Single-Instruction-Multiple-Data (SIMD) architecture, and a number of features that improve performance and programmability. The apparatus includes a...
6058466 System for allocation of execution resources amongst multiple executing processes  
A system of executing coded instructions in a dynamically configurable multiprocessor having shared execution resources including steps of placing a first processor in an active state upon booting...
6047115 Method for configuring FPGA memory planes for virtual hardware computation  
A dynamically reconfigurable FPGA includes an array of tiles on a logic plane and a plurality of memory planes. Each tile has associated storage elements on each memory plane, called local memory....
6023742 Reconfigurable computing architecture for providing pipelined data paths  
A configurable computing architecture (10) has its functionality controlled by a combination of static and dynamic control, wherein the configuration is referred to as static control and...
6002851 Method and apparatus for node pruning a multi-processor system for maximal, full connection during recovery  
A method and apparatus for achieving maximal, full connection in a multi-processor system having a plurality of processors. Each of the multiple processors has a respective memory. The invention...
5999734 Compiler-oriented apparatus for parallel compilation, simulation and execution of computer programs and hardware models  
A distributed, compiler-oriented database is disclosed with operating modes including parallel compilation, parallel simulation and parallel execution of computer programs and hardware models. The...
5960211 Data formatting method and apparatus for a data processing array  
Data is reformatted in a memory external to the processing elements of a processing array, relieving the processing array of this task and allowing it to perform its data processing functions more...
5944814 Parallel processing digital audio processing apparatus  
This invention relates to the allocation of object code in multi-processor systems. In particular, techniques are disclosed for efficiently allocating signal processing instructions to a large...
5935230 Multiprocessor arrangement including bus arbitration scheme involving plural CPU clusters that address each other as "phantom" CPUs  
At least two clusters of CPUs are present in a multiprocessor computer system. Each CPU cluster has a given number of CPUs, each CPU having an associated ID such as an ID number. An additional ID...
5931910 System for node address initialization using pointers to designate the first address in selected sets of node addresses corresponding to selected inter-processor communications  
A method of initializing node addresses for use in an electronic switching system comprises the steps of: (a) storing all possible sets of node addresses, each set corresponding to an...
5931938 Multiprocessor computer having configurable hardware system domains  
Global address and data routers interconnect individual system units each having its own processors, memory, and I/O. A domain filter coupled to the routers dynamically defines groups of system...
5890008 Method for dynamically reconfiguring a processor  
A method and apparatus for dynamically reconfiguring a processor involves placing the processor in a first configuration having a first number (m) of strands while the coded instructions comprise...
5862332 Method of data passing in parallel computer  
In response to the issue of a request for processing long data from an application node to a server A, the server A sends a message requesting a server B for the processing of the long data. The...
5862397 Array system architecture of multiple parallel structure processors  
A system of elementary processors in array form organized in accordance with a plurality of nodes with SIMD operation, each having a plurality of elementary processors connected to one another so...
5852740 Polymorphic network methods and apparatus  
A modular, polymorphic network interconnecting a plurality of electronically reconfigurable devices via a modular, polymorphic interconnect, to permit a fixed, physical configuration of operating...
5826095 Method and apparatus for maintaining the order of data items processed by parallel processors  
A data processing system includes two or more parallel processors, a distributor and a combiner. The processors process input data items and generate corresponding output data items. The...
5794059 N-dimensional modified hypercube  
A parallel array processor for massively parallel applications is formed with low power CMOS with DRAWM processing while incorporating processing elements on a single chip, with nodes connected in...
Matches 101 - 150 out of 208 < 1 2 3 4 5 >