Matches 51 - 100 out of 208 < 1 2 3 4 5 >
Match Document Document Title
7174443 Run-time reconfiguration method for programmable units  
A method of run-time reconfiguration of a programmable unit is provided, the programmable unit including a plurality of reconfigurable function cells in a multidimensional arrangement. An event is...
7159099 Streaming vector processor with reconfigurable interconnection switch  
A re-configurable, streaming vector processor ( 100 ) is provided which includes a number of function units ( 102 ), each having one or more inputs for receiving data values and an output for...
7158907 Systems and methods for configuring a test setup  
Methods for configuring a test setup that support reuse of previously defined sub-configuration parameter values without reference to individually-named sub-configuration files are provided. In...
7126214 Reconfigurable processor module comprising hybrid stacked integrated circuit die elements  
A reconfigurable processor module comprising hybrid stacked integrated circuit (“IC”) die elements. In a particular embodiment disclosed herein, a processor module with reconfigurable...
7127590 Reconfigurable VLIW processor  
Disclosed is a computer processor ( 300 ) comprising a plurality of processing units (FU_n) and communication means ( 302 ) by which the plurality of processing units are interconnected. The...
7107329 In networks of interconnected router nodes for routing data traffic, a method of and system for imperceptibly upgrading router node software and the like without traffic interruption  
In networks of interconnected router nodes for forwarding data traffic along a predetermined path of the network, a method of and system for imperceptibly upgrading router node software and the...
7100020 Digital communications processor  
An integrated circuit ( 203 ) for use in processing streams of data generally and streams of packets in particular. The integrated circuit ( 203 ) includes a number of packet processors ( 307, 313,...
7085913 Hub/router for communication between cores using cartesian coordinates  
A method and structure for an integrated circuit is disclosed. The invention includes a plurality of logic cores, a plurality of local hubs connected to said logic cores, and a plurality of global...
7043562 Irregular network  
Irregularities are provided in at least one dimension of a torus or mesh network for lower average path length and lower maximum channel load while increasing tolerance for omitted end-around...
7032103 System and method for executing hybridized code on a dynamically configurable hardware environment  
A system and method for executing previously created run time executables in a configurable processing element array is disclosed. In one embodiment, this system and method begins by identifying at...
7017158 Multi-processor system, data processing system, data processing method, and computer program  
The multi-processor system comprises a plurality of cell processors for performing data processing, a BCMC for broadcasting broadcast data including data used in data processing to the plurality of...
6996504 Fully scalable computer architecture  
A scalable computer architecture capable of performing fully scalable simulations includes a plurality of processing elements (PEs) and a plurality of interconnections between the PEs. In this...
6973559 Scalable hypercube multiprocessor network for massive parallel processing  
A system and method for interconnecting a plurality of processing element nodes within a scalable multiprocessor system is provided. Each processing element node includes at least one processor and...
6957318 Method and apparatus for controlling a massively parallel processing environment  
A method for controlling a processor array by a host computer involves creating a graph of a plurality of nodes using a data connection component, configuring a broadcast tree from a spanning tree...
6941539 Efficiency of reconfigurable hardware  
The present invention includes a method of computing a function array in reconfigurable hardware that includes forming in the reconfigurable hardware a first delay queue and a second delay queue,...
6934835 Building block removal from partitions  
Removing building blocks from partitions to which they have been bound is disclosed. A building block of a platform is removed from a partition of the platform by first halting activity by the...
6920545 Reconfigurable processor with alternately interconnected arithmetic and memory nodes of crossbar switched cluster  
A reconfigurable processor architecture. A reconfigurable processor is an array of a multiplicity of various functional elements, between which the interconnections may be programmably configured....
6883084 Reconfigurable data path processor  
A reconfigurable data path processor comprises a plurality of independent processing elements. Each of the processing elements advantageously comprising an identical architecture. Each processing...
6874079 Adaptive computing engine with dataflow graph based sequencing in reconfigurable mini-matrices of composite functional blocks  
Aspects of a method and system for digital signal processing within an adaptive computing engine are described. These aspects include a mini-matrix, the mini-matrix comprising a set of composite...
6865661 Reconfigurable single instruction multiple data array  
A reconfigurable single instruction multiple data array includes a plurality of processing cells; a serial data bus with at least one line dedicated to each cell; each cell including an...
6859869 Data processing system  
A data processing system, wherein a data flow processor (DFP) integrated circuit chip is provided which comprises a plurality of orthogonally arranged homogeneously structured cells, each cell...
6847365 Systems and methods for efficient processing of multimedia data  
A media processing system is provided including a DRAM that includes a plurality of storage locations for storing digital data being processed by said media processing system, said digital data...
6836839 Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements  
The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of...
6834340 Mechanism to safely perform system firmware update in logically partitioned (LPAR) machines  
A method for managing system firmware in a data processing system having a plurality of logical partitions is provided. Responsive to a request to update the system firmware from a first logical...
6810434 Multimedia interface having a processor and reconfigurable logic  
An integrated circuit architecture for multimedia processing. A single integrated circuit (IC) operates as a system or subsystem, and is adaptable to processing a variety of multimedia algorithms,...
6795909 Methods and apparatus for ManArray PE-PE switch control  
Processing element to processing element switch connection control is described using a receive model that precludes communication hazards from occurring in a synchronous MIMD mode of operation....
6769056 Methods and apparatus for manifold array processing  
A manifold array topology includes processing elements, nodes, memories or the like arranged in clusters. Clusters are connected by cluster switch arrangements which advantageously allow changes of...
6766449 Method and apparatus for dynamic processor configuration by limiting a processor array pointer  
A method and system provides for changing processor configuration during operation of the processor system. The method and system include a control logic circuit where the control logic circuit...
6754802 Single instruction multiple data massively parallel processor systems on a chip and system using same  
A single chip active memory includes a plurality of memory stripes, each coupled to a full word interface and one of a plurality of processing element (PE) sub-arrays. The large number of couplings...
6754805 Method and apparatus for configurable multi-cell digital signal processing employing global parallel configuration  
An improved mechanism for performing different types of digital signal processing functions, including correlation, sorting, and filtering operations. The mechanism includes a plurality of...
6751722 Local control of multiple context processing elements with configuration contexts  
A method and apparatus for providing local control of processing elements in a network of multiple context processing elements (MCPEs). A MCPE stores configuration memory contexts and maintains...
6745240 Method and apparatus for configuring massively parallel systems  
A method, apparatus, article of manufacture, and a memory structure for configuring a massively parallel processing system is disclosed. The method comprises the steps of selecting one of the...
6738891 Array type processor with state transition controller identifying switch configuration and processing element instruction address  
To execute all processing in an array section of an array-type processor, each processor must execute processing of different types, i.e., processing of an operating unit and processing of a random...
6732253 Loop handling for single instruction multiple datapath processor architectures  
A method of controlling the enabling of processor datapaths in a SIMD processor during a loop processing operation is described. The information used by the method includes an allocation between...
6732068 Memory circuit for use in hardware emulation system  
A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic...
6718414 Function modification in a write-protected operating system  
An apparatus and method are disclosed for runtime modification of called functions within a write-protected operating system. The access state of a processor is altered to allow modification of the...
6691301 System, method and article of manufacture for signal constructs in a programming language capable of programming hardware architectures  
A system, method and article of manufacture are provided for using a dynamic object in a programming language. In general, an object is defined with an associated first value and second value. The...
6684318 Intermediate-grain reconfigurable processing device  
A programmable integrated circuit utilizes a large number of intermediate-grain processing elements which are multibit processing units arranged in a configurable mesh. The coarse-grain resources,...
6681341 Processor isolation method for integrated multi-processor systems  
A processor isolation technique enhances debug capability in a highly integrated multiprocessor circuit containing a programmable arrayed processing engine for efficiently processing transient data...
6681316 Network of parallel processors to faults-tolerant towards said processors and reconfiguration method applicable to such a network  
This invention relates to a network of parallel elementary processors, tolerant to the faults of these processors including said elementary processors, spare elementary processors, elements...
6658564 Reconfigurable programmable logic device computer system  
A reconfigurable computer system based on programmable logic is provided. A system design language may be used to write applications. The applications may be automatically partitioned into software...
6653859 Heterogeneous integrated circuit with reconfigurable logic cores  
A heterogeneous integrated circuit having a digital signal processor and two programmable logic cores, PLCs. An AMBA AHB couples the cores and most other functional units on the IC. The PLCs are...
6622163 System and method for managing storage resources in a clustered computing environment  
A system and method for managing storage resources in a clustered computing environment are disclosed. A method incorporating teachings of the present disclosure may include holding a reservation...
6598146 Data-processing arrangement comprising a plurality of processing and memory circuits  
A data-processing arrangement comprises a plurality of elementary circuits such as processing circuits [PRC] and memory circuits [MEM]. The data-processing arrangement further comprises a...
6567837 Object oriented processor arrays  
An object oriented processor array includes a library of functional objects which are instantiated by commands through a system object and which communicate via a high level language. The object...
6567909 Parallel processor system  
A parallel processor system is constructed to include a pair of parallel buses ( 2, 3 ), pipeline buses ( 9 ), a plurality of processor nodes ( 1 - 1 to 1 -N) having functions of carrying out an...
6553479 Local control of multiple context processing elements with major contexts and minor contexts  
A method and apparatus for providing local control of processing elements in a network of multiple context processing element are provided. A multiple context processing element is configured to...
6526461 Interconnect chip for programmable logic devices  
A method and apparatus for interconnecting multiple programmable logic devices. In a preferred embodiment of the invention, an interconnect chip couples one programmable logic device to another...
6496858 Remote reconfiguration of a secure network interface  
The present invention discloses a initializing and reconfiguring a network interface device connecting a client computer system to an external network. The network interface device is configured...
6487678 Recovery procedure for a dynamically reconfigured quorum group of processors in a distributed computing system  
Dynamic reconfiguration of a quorum group of processors and recovery procedure therefore are provided for a shared nothing distributed computing system. Dynamic reconfiguration proceeds...
Matches 51 - 100 out of 208 < 1 2 3 4 5 >