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7584332 Computer systems with lightweight multi-threaded architectures  
Embodiments of the present invention provide a class of computer architectures generally referred to as lightweight multi-threaded architectures (LIMA). Other embodiments may be described and claimed.
7581079 Processor composed of memory nodes that execute memory access instructions and cooperate with execution nodes to execute function instructions  
A shared memory network for communicating between processors using store and load instructions is described. A new processor architecture which may be used with the shared memory network is also...
7539845 Coupling integrated circuits in a parallel processing environment  
An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the...
7519793 Facilitating inter-DSP data communications  
A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate...
7503046 Method of obtaining interleave interval for two data values  
A method of determining an interleave pattern for n lots of A and y lots of B, when n plus y equals a power of two such that the expression 2 z −n may be used to represent the value of y,...
7493468 Method for broadcasting instructions/data to a plurality of processors in a multiprocessor device via aliasing  
A method for broadcasting instructions/data to a plurality of processors in a multiprocessor device via aliasing is provided. In order to broadcast data to a plurality of processors, a control...
7461236 Transferring data in a parallel processing environment  
An integrated circuit includes a plurality of tiles. Each tile comprises a processor; and a switch including switching circuitry to forward data over data paths from other tiles to the processor...
7451292 Methods for transmitting data across quantum interfaces and quantum gates using same  
Quantum gaps exist between an origin and a destination that heretofore have prevented reliably utilizing the advantages of quantum computing. To predict the outcome of instructions with precision,...
7428629 Memory request / grant daemons in virtual nodes for moving subdivided local memory space from VN to VN in nodes of a massively parallel computer system  
A memory management mechanism a nodal having multiple processors in a massively parallel computer system dynamically configures nodal memory on demand. A respective variable-sized subdivision of...
7409529 Method and apparatus for a shift register based interconnection for a massively parallel processor array  
A system and method for using wider data paths within Processing Elements (PEs) of a Massively Parallel Array (MPP) to speed the computational performance of the PEs and the MPP array while still...
7409528 Digital signal processing architecture with a wide memory bandwidth and a memory mapping method thereof  
A DSP (Digital Signal Processing) architecture with a wide memory bandwidth and a memory mapping method thereof. The DSP architecture includes: a first communication port; first, second, and third...
7404066 Active memory command engine and method  
A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array...
7398368 Atomic operation involving processors with different memory transfer operation sizes  
Atomic operations may be implemented on a processor system having a main memory and two or more processors including a power processor element (PPE) and a synergistic processor element (SPE) that...
7386689 Method and apparatus for connecting a massively parallel processor array to a memory array in a bit serial manner  
A method and apparatus for connecting the processor array of an MPP array to a memory such that data conversion by software is not necessary, and the data can be directly stored in either a normal...
7370046 Sort processing method and sort processing apparatus  
Disclosed are a sort processing method and a sort processing apparatus, which, in a computer or data processing, compare magnitudes of pieces of data input by hardware, rearrange the pieces of data...
7363304 Method and system for providing a hardware sort for a large number of items  
A method and system for sorting a number of items in a computer system. The sort is based on a plurality of values of a key. Each item has a value of the plurality of values. The method and system...
7272691 Interconnect switch assembly with input and output ports switch coupling to processor or memory pair and to neighbor ports coupling to adjacent pairs switch assemblies  
A data processor apparatus comprises a plurality of processor elements, a memory having a plurality of parts, and a first switching element associated with the first processor element for...
7237087 Reconfigurable multidimensional array processor allowing runtime reconfiguration of selected individual array cells  
An expanded arithmetic and logic unit (EALU) with special extra functions is integrated into a configurable unit for performing data processing operations. The EALU is configured by a function...
7149876 Method and apparatus for a shift register based interconnection for a massively parallel processor array  
A system and method for using wider data paths within Processing Elements (PEs) of a Massively Parallel Array (MPP) to speed the computational performance of the PEs and the MPP array while still...
7100020 Digital communications processor  
An integrated circuit ( 203 ) for use in processing streams of data generally and streams of packets in particular. The integrated circuit ( 203 ) includes a number of packet processors ( 307, 313,...
7072357 Flexible buffering scheme for multi-rate SIMD processor  
A single instruction, multiple data (SIMD) architecture for controlling the processing of plurality of data streams in a digital subscriber line (DSL) system has a memory for storing the data from...
7069416 Method for forming a single instruction multiple data massively parallel processor system on a chip  
A single chip active memory includes a plurality of memory stripes, each coupled to a full word interface and one of a plurality of processing element (PE) sub-arrays. The large number of couplings...
7065215 Microprocessor with program and data protection function under multi-task environment  
In a microprocessor, a program key for decrypting a program and a data key for encrypting/decrypting data processed by the program are handled as cryptographically inseparable pair inside the...
7058540 Method and system for accelerating power complementary cumulative distribution function measurements  
Data values representing the (I 2 +Q 2 ) values are converted to floating-point representations and a histogram of the floating-point numbers is generated. The count for each histogram bin in the...
7020764 Semiconductor processing device  
A useful semiconductor processing device (LSI) is capable of implementing the precise setting of signals at the final stage of user system development and enabling the user to build a logic circuit...
6986020 Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller  
Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an...
6967950 Pull transfers and transfer receipt confirmation in a datapipe routing bridge  
In a network of digital signal processor nodes connected in a peer-to-peer relationship, a data packet sent to a node causes a return transmission from that node. The requester digital signal...
6901491 Method and apparatus for integration of communication links with a remote direct memory access protocol  
In one embodiment, a server is provided. The server includes multiple application processor chips. Each of the multiple application processor chips includes multiple processing cores. Multiple...
6839648 Systems for providing zero latency, non-modulo looping and branching of test pattern data for automatic test equipment  
An SRAM efficient ATE system that performs high speed nested loops without constraints on loop size or modularity and that loops and/or branches from any vector in a multiple vector accessed word...
6795909 Methods and apparatus for ManArray PE-PE switch control  
Processing element to processing element switch connection control is described using a receive model that precludes communication hazards from occurring in a synchronous MIMD mode of operation....
6754803 Multiprocessor system and address solution method of the same  
In a distributed shared memory type multiprocessor system, even a cell, which has no address solution mechanism, can be used as a constitutional component, so that the multiprocessor system can be...
6754802 Single instruction multiple data massively parallel processor systems on a chip and system using same  
A single chip active memory includes a plurality of memory stripes, each coupled to a full word interface and one of a plurality of processing element (PE) sub-arrays. The large number of couplings...
6732068 Memory circuit for use in hardware emulation system  
A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic...
6728863 Wide connections for transferring data between PE's of an N-dimensional mesh-connected SIMD array while transferring operands from memory  
A single-instruction multiple-data (SIMD) array processor providing enhanced data transfer efficiency. The SIMD array processor includes at least one memory and a plurality of mesh-connected...
6728862 Processor array and parallel data processing methods  
An array of processor elements has multiple instruction streams and multiple data streams broadcast to all of the processor elements. The processor elements are each connected to multiple...
6728841 Conserving system memory bandwidth during a memory read operation in a multiprocessing computer system  
A messaging scheme that conserves system memory bandwidth during a memory read operation in a multiprocessing computer system is described. A source processing node sends a memory read command to a...
6711665 Associative processor  
An associative processor includes a plurality of arrays of content addressable memory (CAM) cells and a plurality of tags registers in a tags logic block. Different tags registers are associated...
6662246 Two-dimensional memory access in image processing systems  
A two-dimensional direct memory access system that maximizes processing resources in image processing systems. The present invention includes a two-dimensional direct memory access machine. Also,...
6654646 Enhanced memory addressing control  
A processing or control system having arrangements for separately and simultaneously generating instruction addresses and data addresses having two bus systems for accessing instruction and data...
6609235 Method for providing a fill pattern for an integrated circuit design  
A method for providing a fill pattern for integrated circuit designs is disclosed. A keepout file having keepout data is generated from a chip design layout file having chip design layout data. The...
6606589 Disk storage subsystem with internal parallel data path and non-volatile memory  
Disclosed is a solid state disk emulator system for significantly improving access time, i.e., improving both the seek time and the rotational latency. The disk emulator complies with the SMD...
6587914 Non-volatile memory capable of autonomously executing a program  
A non-volatile semiconductor memory device that includes an address buffer block, a matrix of memory cells, and an output buffer block. The address buffer block receives input signals external to...
6460131 FPGA input output buffer with registered tristate enable  
In accordance with the present invention, an FPGA input/output buffer including a tristate enable register is provided. A bus line provides the FPGA output through a tristate buffer to the pad or...
6460127 Apparatus and method for signal processing  
An associative signal processing apparatus for processing a plurality of samples of an incoming signal in parallel, the apparatus comprising: (a) an array, of processors, each processor including a...
6449707 Information processing unit, information processing structure unit, information processing structure, memory structure unit and semiconductor memory device  
A data processing unit comprises an input section 1 for inputting first data from the outside, an operation section 2 for operating the first data inputted therefrom, to generate second data, a...
6449664 Two dimensional direct memory access in image processing systems  
A two-dimensional direct memory access system that maximizes processing resources in image processing systems. The present invention includes a two-dimensional direct memory access machine. Also,...
6414368 Microcomputer with high density RAM on single chip  
A microcomputer comprises an integrated circuit device with processor and memory and communication links arranged to provide non-shared connections to similar links of other microcomputers. The...
6405301 Parallel data processing  
A data-processing arrangement for a plurality of parallel data processors is disclosed. An operation carried out by at least one of the parallel processors is defined by an instruction word or...
6404439 SIMD control parallel processor with simplified configuration  
According to the SIMD control parallel processing method for performing common operation in parallel in a plurality of elements, comprising first retaining means for retaining operation data...
6401189 General base state assignment for optimal massive parallelism  
General base hypercube transformations using general base perfect shuffles and Kronecker matrix products are applied to the problem of parallel, to massively parallel processing of sparse matrices....
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