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Document Title |
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7581087 |
Method and apparatus for debugging a multicore system
Techniques for debugging a multicore system with synchronous stop and resume capabilities are described. In one design, an apparatus (e.g., an ASIC) includes first and second processing cores....
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7574581 |
Cross-chip communication mechanism in distributed node topology to access free-running scan registers in clock-controlled components
A method of communicating between processing units on different integrated circuit chips in a multi-processor computer system by issuing a command from a source processing unit to a destination...
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7526631 |
Data processing system with backplane and processor books configurable to support both technical and commercial workloads
A processor book designed to support both commercial workloads and technical workloads based on a dynamic or static mechanism of reconfiguring the external wiring interconnect. The processor book...
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7441098 |
Conditional execution of instructions in a computer
A method of executing instructions in a computer system on operands containing a plurality of packed objects in respective lanes of the operand is described. Each instruction defines an operation...
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7185226 |
Fault tolerance in a supercomputer through dynamic repartitioning
A multiprocessor, parallel computer is made tolerant to hardware failures by providing extra groups of redundant standby processors and by designing the system so that these extra groups of...
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7103639 |
Method and apparatus for processing unit synchronization for scalable parallel processing
The present invention flexibly manages the formation of a partition from a plurality of independently executing cells (discrete hardware entities comprising system resources) in preparation for the...
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7043562 |
Irregular network
Irregularities are provided in at least one dimension of a torus or mesh network for lower average path length and lower maximum channel load while increasing tolerance for omitted end-around...
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6973559 |
Scalable hypercube multiprocessor network for massive parallel processing
A system and method for interconnecting a plurality of processing element nodes within a scalable multiprocessor system is provided. Each processing element node includes at least one processor and...
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6898657 |
Autonomous signal processing resource for selective series processing of data in transit on communications paths in multi-processor arrangements
A multi-processor arrangement having an interprocessor communication path between each of every possible pair of processors, in addition to I/O paths to and from the arrangement, having signal...
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6873287 |
Signal processing arrangement
The present invention relates to a method and an arrangement suitable for embedded signal processing, comprising a number of computational units ( 100 ), each computational unit comprising a number...
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6769056 |
Methods and apparatus for manifold array processing
A manifold array topology includes processing elements, nodes, memories or the like arranged in clusters. Clusters are connected by cluster switch arrangements which advantageously allow changes of...
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6754892 |
Instruction packing for an advanced microprocessor
A process for packing an instruction word including providing a word value representing an instruction word into which an operation is to be fit be equal to some initial value having a plurality of...
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6754735 |
Single descriptor scatter gather data transfer to or from a host processor
A processing system includes a processing device and a host processor operatively coupled to the processing device via a system bus, and implements a scatter gather data transfer technique. The...
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6741552 |
Fault-tolerant, highly-scalable cell switching architecture
Generally speaking, the cell switching architecture of the present invention offers a powerful, simple, and in many ways elegant solution to the problem of providing cost-effective, high-bandwidth,...
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6680915 |
Distributed computing system using virtual buses and data communication method for the same
A router, which is basically a point-to-point communication router, is devised for the BUS-like communication between processors. Therefore, it is named as ‘Virtual Bus’. One processor is...
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6609189 |
Cycle segmented prefix circuits
The poor scalability of existing superscalar processors has been of great concern to the computer engineering community. In particular, the critical-path delays of many components in existing...
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6526375 |
Self-configuring store-and-forward computer network
In a self-configuring store-and-forward computer network, a plurality of processors are each housed in an enclosure having a top surface and a bottom surface. Each processor has an associated block...
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6510539 |
System and method for physically modeling electronic modules wiring
A computer program receives a large plurality of module design parameters and provides as output a graphical representation of the design together with text files that rate module wireability,...
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6487456 |
Method and apparatus for creating a selectable electrical characteristic
A device having a variable output electrical characteristic includes first and second output terminals and a number of switching circuits, each switching circuit having two states. One of the...
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6470441 |
Methods and apparatus for manifold array processing
A manifold array topology includes processing elements, nodes, memories or the like arranged in clusters. Clusters are connected by cluster switch arrangements which advantageously allow changes of...
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6418427 |
Online modifications of dimension structures in multidimensional processing
A method/operator is disclosed that modifies dimension structures and relations during processing in a multidimensional data cube. The online “blowup” operator disclosed uses one or more...
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6356900 |
Online modifications of relations in multidimensional processing
A method/operator is disclosed that adjusts measurements during processing in a multidimensional data cube. The online “depth-of-field” operator disclosed varies the density of points in a...
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6230252 |
Hybrid hypercube/torus architecture
A scalable multiprocessor system includes processing element nodes. A scalable interconnect network includes physical communication links interconnecting the processing element nodes in an...
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6219775 |
Massively parallel computer including auxiliary vector processor
A massively-parallel computer includes a plurality of processing nodes and at least one control node interconnected by a network. The network faciliates the transfer of data among the processing...
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6195738 |
Combined associative processor and random access memory architecture
An architecture combining an associative processor memory array and a random access memory is provided. This combination architecture enables utilizing the parallel processing abilities of the...
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6167502 |
Method and apparatus for manifold array processing
A manifold array topology includes processing elements, nodes, memories or the like arranged in clusters. Clusters are connected by cluster switch arrangements which advantageously allow changes of...
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RE36954 |
SIMD system having logic units arranged in stages of tree structure and operation of stages controlled through respective control registers
In a parallel computer system using a SIMD method constituted by a controller and a plurality of processor elements, each of the processor elements has a storage unit to store data to be processed,...
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6128719 |
Indirect rotator graph network
An interconnection network used for a multiprocessor system. An indirect n-dimensional rotator graph network having a transmission path of arbitrary nodes in a multiprocessor system including n!...
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6038688 |
Node disjoint path forming method for hypercube having damaged node
A node disjoint path forming method for a hypercube having a damaged node which is capable of using unused nodes (surplus nodes) in an n-number of node disjoint paths each having a length of n with...
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5991866 |
Method and system for generating a program to facilitate rearrangement of address bits among addresses in a massively parallel processor system
A system and method for generating a program to enable reassignment of data items among processors in a massively-parallel computer to effect a predetermined rearrangement of address bits. The...
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5963745 |
APAP I/O programmable router
A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processor memory...
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5842034 |
Two dimensional crossbar mesh for multi-processor interconnect
A parallel processor array with a two-dimensional crossbar switch architecture. Individual processing elements are configured as clusters of processors, wherein the individual processing elements...
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5826033 |
Parallel computer apparatus and method for performing all-to-all communications among processing elements
A parallel computer and all-to-all communications method. A plurality of processors are connected in an n-dimensional torus network, to provide an optimum communication method and apparatus for...
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5822605 |
Parallel processor system with a broadcast message serializing circuit provided within a network
In a parallel processor system comprising a plurality of processor elements constituting a network, a source processor element wishing to broadcast data to a plurality of destination processor...
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5794059 |
N-dimensional modified hypercube
A parallel array processor for massively parallel applications is formed with low power CMOS with DRAWM processing while incorporating processing elements on a single chip, with nodes connected in...
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5740463 |
Information processing system and method of computation performed with an information processing system
Intercommunication of data between adjacent element processors (3) is performed through a memory unit (6) which is independently accessible to the respective element processors (3) without...
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5689722 |
Multipipeline multiprocessor system
The multipipeline multiprocessor includes communication hardware and parallel communication algorithms that are free of contention but also optimal in the sense that communication time is minimized...
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5675823 |
Grain structured processing architecture device and a method for processing three dimensional volume element data
According to the present invention, a 3D connectivity-conserved grain-structured processing architecture uses connectable massively parallel processors. A 3D grain-structured processing...
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5669008 |
Hierarchical fat hypercube architecture for parallel processing systems
A hierarchical fat hypercube topology provides an infrastructure for implementing a multi-processor system at a plurality of levels. A first level is comprised of a plurality of n-dimensional...
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5642524 |
Methods for generating N-dimensional hypercube structures and improved such structures
A method of generating designs for N-dimensional hypercube structures along with the resulting structures, wherein the positive integer N defines the binary space dimension of the representative...
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5617577 |
Advanced parallel array processor I/O connection
A fast I/O for a multi-PME computer system provides a way to break into a network coupling to alternate network couplings. The system coupling is called a zipper. Our I/O zipper concept can be used...
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5598570 |
Efficient data allocation management in multiprocessor computer system
The present invention comprises a computer system having a plurality of processors configured in an architecture having at least two subgraphs wherein at least a first subgraph and a second...
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5560027 |
Scalable parallel processing systems wherein each hypernode has plural processing modules interconnected by crossbar and each processing module has SCI circuitry for forming multi-dimensional network with other hypernodes
A processing system 100 is provided which includes first and second hypernodes 101, each of the hypernodes 101 having at least first and second coherent interfaces 106. At least first and second...
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5430887 |
Cube-like processor array architecture
According to the present invention, a 3D connectivity-conserved grain-structured processing architecture uses connectable massively parallel processors. A 3D grain-structured processing...
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5430885 |
Multi-processor system and co-processor used for the same
A multi-processor system for multidimensional image signal processing includes a plurality of co-processors and a host processor which issues processor numbers and a command to the co-processors...
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5420982 |
Hyper-cube network control system having different connection patterns corresponding to phase signals for interconnecting inter-node links and between input/output links
A network control system in a hyper cube type network having 2 n nodes (n>0, integer), each of the nodes being arranged on an apex of a cube and having n sets of links for interconnecting other...
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5379440 |
Parallel processor with array of clustered processing elements having inputs seperate from outputs and outputs limited to a maximum of two per dimension
A processor is provided (FIG. 1) comprising a plurality of processing elements (10) arranged into D dimensions and divided into clusters (11), wherein all elements in a cluster have a bus (13) for...
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5367692 |
Parallel computer system including efficient arrangement for performing communications among processing node to effect an array transposition operation
A processing element array and a controller. The processing element array comprises a plurality of processing element nodes interconnected by a plurality of communications links in the form of a...
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5345578 |
Competitive snoopy caching for large-scale multiprocessors
A system and method of satisfying read and write requests is used in a system having a plurality of cache-equipped processors coupled into a hypercube structure via buses, where each processor is...
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5341504 |
Multi-dimensional structured computer system
A plurality of processors have a plurality pairs of input ports and output ports, and are constituted in a looped manner by connecting the output ports and the input ports of the same pairs of any...
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