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7602423 |
Integrated circuit for a digital camera system
A monolithic integrated circuit includes programmable processing circuitry. An image sensor interface is connected to the processing circuitry and is configured to receive signals from an image...
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7599998 |
Message handling communication between a source processor core and destination processor cores
A data processing apparatus comprises at least one source processor core, at least two destination processor cores, a message handler and a bus arrangement providing a data communication path...
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7595659 |
Logic cell array and bus system
A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for...
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7594060 |
Data buffer allocation in a non-blocking data services platform using input/output switching fabric
Data buffering allocation in a microprocessor complex for a request of memory allocation is supported through a remote buffer batch allocation protocol. The separation of control and data placement...
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7590821 |
Digital signal processing integrated circuit with I/O connections
A digital signal processing integrated circuit contains an array of interconnected and programmed or programmable digital signal processors ( 10 ). Configurable multiplexing circuits ( 12 ), are...
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7581081 |
Systems and methods for software extensible multi-processing
A system for processing applications includes processor nodes and links interconnecting the processor nodes. Each node includes a processing element, a software extensible device, and a...
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7581079 |
Processor composed of memory nodes that execute memory access instructions and cooperate with execution nodes to execute function instructions
A shared memory network for communicating between processors using store and load instructions is described. A new processor architecture which may be used with the shared memory network is also...
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7577820 |
Managing data in a parallel processing environment
An integrated circuit comprises a plurality of tiles. Each tile comprises a processor including a storage module, wherein the processor is configured to process multiple streams of instructions, a...
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7565287 |
Methods and apparatus for efficient vocoder implementations
Techniques for implementing vocoders in parallel digital signal processors are described. A preferred approach is implemented in conjunction with the BOPS® Manifold Array (ManArray™) processing...
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7539845 |
Coupling integrated circuits in a parallel processing environment
An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the...
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7526631 |
Data processing system with backplane and processor books configurable to support both technical and commercial workloads
A processor book designed to support both commercial workloads and technical workloads based on a dynamic or static mechanism of reconfiguring the external wiring interconnect. The processor book...
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7515899 |
Distributed grid computing method utilizing processing cycles of mobile phones
Additional computing power is captured using the idle processing power of mobile phones incorporated into a grid computing system, wherein the system is capable of pushing projects out to available...
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7508776 |
Controlling method and device for data transmission
A controlling method and device for data transmission including the steps of providing a system bus for connecting a first transmission channel and a second transmission channel with a command...
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7503046 |
Method of obtaining interleave interval for two data values
A method of determining an interleave pattern for n lots of A and y lots of B, when n plus y equals a power of two such that the expression 2 z −n may be used to represent the value of y,...
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7502844 |
Abnormality indicator of a desired group of resource elements
A monitoring system provided according to an aspect of the present invention enables a user to specify one or more resource elements as a group, and compute an Abnormality Index that represents the...
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7477608 |
Methods for routing packets on a linear array of processors
There is provided a method for routing packets on a linear of N processors connected in a nearest neighbor configuration. The method includes the step of, for each end processor of the array,...
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7472051 |
Dependable microcontroller, method for designing a dependable microcontroller and computer program product therefor
A microcontroller comprising a central processing unit and a further fault processing unit suitable for performing validation of operations of said central processing unit. The further fault...
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7471643 |
Loosely-biased heterogeneous reconfigurable arrays
A heterogeneous array includes clusters of processing elements. The clusters include a combination of ALUs and multiplexers linked by direct connections and various general-purpose routing...
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7461236 |
Transferring data in a parallel processing environment
An integrated circuit includes a plurality of tiles. Each tile comprises a processor; and a switch including switching circuitry to forward data over data paths from other tiles to the processor...
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7461234 |
Loosely-biased heterogeneous reconfigurable arrays
A heterogeneous array includes clusters of processing elements. The clusters include a combination of ALUs and multiplexers linked by direct connections and various general-purpose routing...
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7454593 |
Row and column enable signal activation of processing array elements with interconnection logic to simulate bus effect
The present invention relates to the control of an array of processing elements in a parallel processor using row and column select lines. For each column in the array, a column select line...
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7451292 |
Methods for transmitting data across quantum interfaces and quantum gates using same
Quantum gaps exist between an origin and a destination that heretofore have prevented reliably utilizing the advantages of quantum computing. To predict the outcome of instructions with precision,...
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7444276 |
Hardware acceleration system for logic simulation using shift register as local cache
A logic simulation processor stores in a shift register intermediate values generated during the logic simulation. The simulation processor includes multiple processor units and an interconnect...
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7418536 |
Processor having systolic array pipeline for processing data packets
A processor for use in a router, the processor having a systolic array pipeline for processing data packets to determine to which output port of the router the data packet should be routed. In one...
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7406582 |
Resolving crossing requests in multi-node configurations
A method for communicating between nodes of a plurality of nodes is disclosed. Each node includes a plurality of processors and an interconnect chipset. The method issues a request for data from a...
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7406075 |
Crossbar switch, method for controlling operation thereof, and program for controlling operation thereof
A small cost-effective crossbar switch is provided. A switch circuit is disposed in each of a plurality of nodes which are cascade connected with each other in a plurality of stages. Each switch...
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7386689 |
Method and apparatus for connecting a massively parallel processor array to a memory array in a bit serial manner
A method and apparatus for connecting the processor array of an MPP array to a memory such that data conversion by software is not necessary, and the data can be directly stored in either a normal...
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7383242 |
Computer-implemented method and apparatus for item processing
A method and apparatus for item processing is disclosed which provides a stand alone clearing solution having an imaged enable environment for item processing and balancing. The present invention...
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7379418 |
Method for ensuring system serialization (quiesce) in a multi-processor environment
A method of ensuring system serialization in a multiprocessor multi-nodal environment is used to force all processors in a multiprocessor environment to temporarily suspend operations while one...
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7356669 |
Processing system and method for transmitting data
A split protocol transmission method for transmitting data and a communication thread identifier for said data along a communication path from a source functional unit (SFU) to a destination...
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7337249 |
I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures
A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by...
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7315934 |
Data processor and program for processing a data matrix
A data processor has sixteen processing elements that each include a register file and an arithmetic logic unit. A network unit connects between the register files of the processing elements and...
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7308558 |
Multiprocessor data processing system having scalable data interconnect and data routing mechanism
The data interconnect and routing mechanism reduces data communication latency, supports dynamic route determination based upon processor activity level/traffic, and implements an architecture that...
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7302548 |
System and method for communicating in a multi-processor environment
A method for communicating in a multi-processor environment is provided that includes generating a bit at an originating processor associated with a message to be communicated to a destination...
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7299339 |
Super-reconfigurable fabric architecture (SURFA): a multi-FPGA parallel processing architecture for COTS hybrid computing framework
A field programmable gate array includes a virtual bus interface that receives a control word from a host processor over a standard I/O bus. A configurable very long instruction word (VLIW)...
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7275145 |
Processing element with next and previous neighbor registers for direct data transfer
According to some embodiments, a processing element includes (i) a next neighbor register to receive information directly from a previous processing element in a series of processing elements, and...
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7263602 |
Programmable pipeline fabric utilizing partially global configuration buses
A method of associating virtual stripes to physical stripes in a pipelined or ring structure comprises associating a first set of virtual stripes with at least two physical stripes and associating...
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7263597 |
Network device including dedicated resources control plane
The present invention provides a method and apparatus for improving transmission of control information within a network device and between multiple connected network devices. Specifically, a...
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7203816 |
Multi-processor system apparatus allowing a compiler to conduct a static scheduling process over a large scale system of processors and memory modules
A multi-processor system apparatus allows a compiler to perform a static scheduling action easily and can conduct the transfer of data packets without collision in response to a common pattern of...
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7197624 |
Manifold array processor
An array processor includes processing elements ( 00, 01, 02, 03, 10, 11, 12, 13, 20, 21, 22, 23, 30, 31, 32, 33 ) arranged in clusters (e.g., 44, 46, 48, 50 ) to form a rectangular array ( 40 )....
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7185175 |
Configurable bi-directional bus for communicating between autonomous units
Processing units (PUs) are coupled with a gated bi-directional bus structure that allows the PUs to be cascaded. Each PUn has communication logic and function logic. Each PUn is physically coupled...
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7185174 |
Switch complex selectively coupling input and output of a node in two-dimensional array to four ports and using four switches coupling among ports
A switching element for switchably coupling a two-dimensional array of circuit elements comprises an input, an output, means for switchably coupling the input to the output; a first input/output...
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7181594 |
Context pipelines
A method of parallel hardware-based multithreaded processing is described. The method includes assigning tasks for packet processing to programming engines and establishing pipelines between...
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7176914 |
System and method for directing the flow of data and instructions into at least one functional unit
A system and method are provided for directing the flow of data and instructions into at least one functional unit. In one embodiment of a system of components defining a plurality of nodes, a...
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7171499 |
Processor surrogate for use in multiprocessor systems and multiprocessor system using same
A processor surrogate ( 320/520 ) is adapted for use in a processing node (S 1 ) of a multiprocessor data processing system ( 300/500 ) having a plurality of processing nodes (P 0 , S 1 ) coupled...
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7098437 |
Semiconductor integrated circuit device having a plurality of photo detectors and processing elements
A semiconductor integrated circuit device, having a plurality of processing elements accommodated on a single semiconductor chip, has a latch circuit and a selecting circuit. The latch circuit is...
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7069372 |
Processor having systolic array pipeline for processing data packets
A processor for use in a router, the processor having a systolic array pipeline for processing data packets to determine to which output port of the router the data packet should be routed. In one...
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7065672 |
Apparatus and methods for fault-tolerant computing using a switching fabric
Apparatus and methods for fault-tolerant computing using an asynchronous switching fabric where at least one of a plurality of redundant data processing elements executing substantially identical...
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7051185 |
Hypercomputer
A computer system comprising a first block which includes multiple processing subsystem, a second block which includes multiple processing subsystem, a third block which includes multiple...
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7043562 |
Irregular network
Irregularities are provided in at least one dimension of a torus or mesh network for lower average path length and lower maximum channel load while increasing tolerance for omitted end-around...
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