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7595659 Logic cell array and bus system  
A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for...
7581079 Processor composed of memory nodes that execute memory access instructions and cooperate with execution nodes to execute function instructions  
A shared memory network for communicating between processors using store and load instructions is described. A new processor architecture which may be used with the shared memory network is also...
7577823 Wake-up and sleep conditions of processors in a multi-processor system  
The present invention relates to a multi-processor computer system comprising at least two processors for parallel execution of processes, at least two cache memory units, each being...
7577820 Managing data in a parallel processing environment  
An integrated circuit comprises a plurality of tiles. Each tile comprises a processor including a storage module, wherein the processor is configured to process multiple streams of instructions, a...
7571300 Modular distributive arithmetic logic unit  
A memory system includes a plurality of memory blocks, each having a dedicated local arithmetic logic unit (ALU). A data value having a plurality of bytes is stored such that each of the bytes is...
7568084 Semiconductor integrated circuit including multiple basic cells formed in arrays  
A basic cell capable of a fixed operating frequency regardless of the configuration information, which is also capable of effectively utilizing the arithmetic logic circuit within the cell in a LSI...
7565287 Methods and apparatus for efficient vocoder implementations  
Techniques for implementing vocoders in parallel digital signal processors are described. A preferred approach is implemented in conjunction with the BOPS® Manifold Array (ManArray™) processing...
7558943 Processing unit for broadcast parallel processing  
A processing unit includes a control processor and a plurality of element processors having register files. At least two of the element processors pre-receive different parameters, store the...
7555637 Multi-port read/write operations based on register bits set for indicating select ports and transfer directions  
A computer ( 12 ) having multiple data paths ( 38 a - d ) connecting to other devices, which may be similar computers. A register ( 40 d ) is provided that has bits ( 110 ) programmatically...
7555630 Method and apparatus to provide efficient communication between multi-threaded processing elements in a processor unit  
A context forwarding bus efficiently communicates control and data between processing elements in a processor unit having a plurality of processing elements. Control and data information is...
7555566 Massively parallel supercomputer  
A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application...
7552312 Identifying messaging completion in a parallel computer by checking for change in message received and transmitted count at each node  
Methods, parallel computers, and products are provided for identifying messaging completion on a parallel computer. The parallel computer includes a plurality of compute nodes, the compute nodes...
7539845 Coupling integrated circuits in a parallel processing environment  
An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the...
7532244 High-speed vision sensor  
A high-speed vision sensor includes: an analog-to-digital converter array 13 , in which one analog-to-digital converter 210 is provided in correspondence with all the photodetector elements 120...
7523292 Array-type processor having state control units controlling a plurality of processor elements arranged in a matrix  
A multiplicity of processor elements, which both individually execute data processing in accordance with instruction codes that have been set as data and for which mutual connection relations are...
7519975 Method and apparatus for exception handling in a multi-processing environment  
A method and apparatus for exception handling in a multi-processor environment are described. In an embodiment, a method for handling a number of exceptions within a processor in a multi-processing...
7516300 Active memory processing array topography and method  
An integrated active memory device includes an array of processing elements coupled to a dynamic random access memory device and to a component supplying instructions to the processing elements....
7515899 Distributed grid computing method utilizing processing cycles of mobile phones  
Additional computing power is captured using the idle processing power of mobile phones incorporated into a grid computing system, wherein the system is capable of pushing projects out to available...
7487271 Method and apparatus using buffer pools and arrays of buffer pointers for sharing memory in a multiprocessor system  
A multiprocessor system ( 100 ) for sharing memory has a memory ( 102 ), and two or more processors ( 104 ). The processors are programmed to establish ( 202 ) memory buffer pools between the...
7478222 Programmable pipeline array  
Disclosed is an array of programmable data-processing cells configured as a plurality of cross-connected pipelines. An apparatus includes cells capable of performing data-processing functions...
7472392 Method for load balancing an n-dimensional array of parallel processing elements  
One aspect of the present invention relates to a method for balancing the load of an n-dimensional array of processing elements (PEs), wherein each dimension of the array includes the processing...
7471643 Loosely-biased heterogeneous reconfigurable arrays  
A heterogeneous array includes clusters of processing elements. The clusters include a combination of ALUs and multiplexers linked by direct connections and various general-purpose routing...
7461236 Transferring data in a parallel processing environment  
An integrated circuit includes a plurality of tiles. Each tile comprises a processor; and a switch including switching circuitry to forward data over data paths from other tiles to the processor...
7461235 Energy-efficient parallel data path architecture for selectively powering processing units and register files based on instruction type  
Provided is a parallel data path architecture for high energy efficiency. In this architecture, a plurality of parallel process units and a plurality of function units of the process units are...
7461234 Loosely-biased heterogeneous reconfigurable arrays  
A heterogeneous array includes clusters of processing elements. The clusters include a combination of ALUs and multiplexers linked by direct connections and various general-purpose routing...
7447872 Inter-chip processor control plane communication  
An inter-chip communication (ICC) mechanism enables any processor in a pipelined arrayed processing engine to communicate directly with any other processor of the engine over a low-latency...
7441100 Processor synchronization in a multi-processor computer system  
A method for synchronizing a plurality of processors of a multi-processor computer system on a synchronization point is disclosed. The method includes triggering a first set of processors, using a...
7418536 Processor having systolic array pipeline for processing data packets  
A processor for use in a router, the processor having a systolic array pipeline for processing data packets to determine to which output port of the router the data packet should be routed. In one...
7412586 Switch memory architectures  
The present invention provides a switch memory architecture (SMA) consisting of: (i) processing elements (PE) (ii) memory banks (MB), and (iii) interconnect switches (ISWITCH). The present...
7404066 Active memory command engine and method  
A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array...
7389403 Adaptive computing ensemble microprocessor architecture  
An Adaptive Computing Ensemble (ACE) includes a plurality of flexible computation units as well as an execution controller to allocate the units to Computing Ensembles (CEs) and to assign threads...
7376811 Method and apparatus for performing computations and operations on data using data steering  
A data processing system architecture is based upon a hardware engine that includes a plurality of functional units and data routing units that interconnect the functional units. The hardware...
7376765 Apparatus and method for storage processing with split data and control paths  
A system including a storage processing device with an input/output module. The input/output module has port processors to receive and transmit network traffic. The input/output module also has a...
7373432 Programmable circuit and related computing machine and method  
A programmable circuit receives configuration data from an external source, stores the firmware in a memory, and then downloads the firmware from the memory. Such a programmable circuit allows a...
7355601 System and method for transfer of data between processors using a locked set, head and tail pointers  
A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task...
7318143 Reuseable configuration data  
An information processor for executing a program comprising a plurality of separate program instructions is provided. The processor comprises processing logic operable to individually execute said...
7315933 Re-configurable circuit and configuration switching method  
The present invention is a re-configurable circuit capable of reducing latency by selecting a route for skipping the FF of an operation unit and outputting data to a connection destination...
7313788 Vectorization in a SIMdD DSP architecture  
A method for determining vectorization configurations in a computer processor architecture, the method including identifying a vectorizable loop in a computer program, identifying a memory access...
7299339 Super-reconfigurable fabric architecture (SURFA): a multi-FPGA parallel processing architecture for COTS hybrid computing framework  
A field programmable gate array includes a virtual bus interface that receives a control word from a host processor over a standard I/O bus. A configurable very long instruction word (VLIW)...
7290157 Configurable processor with main controller to increase activity of at least one of a plurality of processing units having local program counters  
A processor comprises a main controller (CTR 11 ) and a plurality of processing units ( 1–9 ). Each processing unit ( 1–9 ) has a local controller (CTR 1 –CTR 9 ) and at least one functional...
7287146 Array-type computer processor  
An array-type computer processor stops, with a plurality of computer programs held, a state control unit and a data-path unit, upon input of event data for task switching. The array-type computer...
7275145 Processing element with next and previous neighbor registers for direct data transfer  
According to some embodiments, a processing element includes (i) a next neighbor register to receive information directly from a previous processing element in a series of processing elements, and...
7237086 Configuring a management module through a graphical user interface for use in a computer system  
A customization program for use in customizing a baseboard management controller used for monitoring operation of various computer system components is disclosed. A user interacts with the...
7237045 Apparatus and method for storage processing through scalable port processors  
A system including a storage processing device with an input/output module. The input/output module has port processors to receive and transmit network traffic. The input/output module also has a...
7231464 Management system for multimodule multiprocessor machines  
The present invention relates to a global management system for a multimodule, multiprocessor machine (PK). The system is characterized in that it comprises an independent module (SM) dedicated to...
7202873 Specific scene image selecting apparatus, computer program and computer readable medium on which the computer program is recorded  
An image selecting apparatus includes a designation receiving portion which receives designation of a desired specific scene, an input receiving portion which receives input of image data...
7197623 Multiple processor cellular radio  
Protocol processor intended to be associated with at least one main processor of a system with a view to the execution of tasks to which the main processor is not suited. The Protocol Processor...
7194598 System and method using embedded microprocessor as a node in an adaptable computing machine  
The present invention provides an adaptive computing engine (ACE) that includes processing nodes having different capabilities such as arithmetic nodes, bit-manipulation nodes, finite state machine...
7191310 Parallel processor and image processing apparatus adapted for nonlinear processing through selection via processor element numbers  
A parallel processor includes a global processor which interprets a program and controls the entirety of the parallel processor. A processor-element block includes a plurality of processor elements...
7167976 Interface for integrating reconfigurable processors into a general purpose computing system  
The present invention describes a method and system for an interface for integrating reconfigurable processors into a general purpose computing system. In particular, the system resides in a...
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