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8185896 |
Method for data processing using a multi-tiered full-graph interconnect architecture
A method is provided for implementing a multi-tiered full-graph interconnect architecture. In order to implement a multi-tiered full-graph interconnect architecture, a plurality of processors are...
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8175015 |
WiMAX MAC
A media access control (MAC) processor includes a programmable controller and a memory coupled to the programmable controller to store machine readable instructions for implementing MAC functions...
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8176145 |
System and method for providing insurance data processing services via a user interface
A system architecture for providing remote access to insurance applications from a remote location is provided, including: a presentation layer located at the remote location that provides tools...
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8149234 |
Picture processing using a hybrid system configuration
A system is presented that is configured to reduce power consumption when performing processing tasks. The system includes a first processing entity capable of performing a set of operations, and a...
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8140731 |
System for data processing using a multi-tiered full-graph interconnect architecture
A system is provided for implementing a multi-tiered full-graph interconnect architecture. In order to implement a multi-tiered full-graph interconnect architecture, a plurality of processors are...
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8122269 |
Regulating power consumption in a multi-core processor by dynamically distributing power and processing requests by a managing core to a configuration of processing cores
Methods, systems, and design structures for providing power-regulated multi-core processing. The method includes determining a configuration of processing cores for optimal power consumption. The...
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8122230 |
Using a processor identification instruction to provide multi-level processor topology information
Embodiments of an invention for using a processor identification instruction to provide multi-level processor topology information are disclosed. In one embodiment, a processor includes decode...
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8122156 |
Method and computer for processing an operation command in a computer
A method is provided for processing operation command in a computer that has a display and a host which includes a first display processing unit for local displaying and a second display processing...
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8117351 |
Serial parallel interface for data word architecture
Subject matter disclosed herein relates to techniques involving transitioning serial data into a serial parallel interface.
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8108846 |
Compiling scalar code for a single instruction multiple data (SIMD) execution engine
A mechanism is provided for performing scalar operations using a SIMD data parallel execution unit. With the mechanisms of the illustrative embodiments, scalar operations in application code are...
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8099533 |
Controller and a method for controlling the communication between a processor and external peripheral device
The present invention relates to a data processing system based on a multithreaded operating system. The data processing system comprises at least one processor (PROC) for processing data based on...
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8063909 |
Systems and methods for providing intermediate targets in a graphics system
Intermediate target(s) are utilized in connection with computer graphics in a computer system. In various embodiments, intermediate memory buffers in video memory are utilized to allow serialized...
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8065536 |
Dual mode power-saving computing system
The present invention relates to a data processing system comprising both a high performance computing sub-system having typical high power consumption and a low performance subsystem requiring...
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8065356 |
Datapipe synchronization device
A programmable element for data processing comprises a crosspoint switch (318), a mathematical operation module (320), and a plurality of data hold modules (604,606). Each of the data hold modules...
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8041933 |
Method and apparatus for selectively enabling a microprocessor-based system
A system for selectively enabling a microprocessor-based system is disclosed. State information that describes the operating conditions or circumstances under which a user intends to operate the...
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8010953 |
Method for compiling scalar code for a single instruction multiple data (SIMD) execution engine
Performing scalar operations using a SIMD data parallel execution unit is provided. With the mechanisms of the illustrative embodiments, scalar operations in application code are identified that...
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7996617 |
Multithreaded clustered microarchitecture with dynamic back-end assignment
A multithreaded clustered microarchitecture with dynamic back-end assignment is presented. A processing system may include a plurality of instruction caches and front-end units each to process an...
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7979673 |
Method and apparatus for matrix decompositions in programmable logic devices
A processor is adapted for performing a QR-decomposition. The processor has a program memory, a program controller, connected to the program memory to receive program instructions, and at least one...
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7970961 |
Method and apparatus for distributed direct memory access for systems on chip
A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct...
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7962760 |
Method and apparatus for selectively enabling a microprocessor-based system
A system for selectively enabling a microprocessor-based system is disclosed. State information that describes the operating conditions or circumstances under which a user intends to operate the...
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7953912 |
Guided attachment of accelerators to computer systems
A method of guided attachment of hardware accelerators to slots of a computing system includes dividing a first group of hardware accelerators into a plurality of priority classes, dividing a first...
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7949853 |
Two dimensional addressing of a matrix-vector register array
A processor for processing matrix data. The processor includes M independent vector register files which are adapted to collectively store a matrix of L data elements. Each data element has B...
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7948496 |
Processor architecture with wide operand cache
A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of...
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7934031 |
Reshuffled communications processes in pipelined asynchronous circuits
An asynchronous logic family of circuits which communicate on delay-insensitive flow-controlled channels with 4-phase handshakes and 1 of N encoding, compute output data directly from input data...
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7932910 |
System and software for performing matrix multiply extract operations
A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of...
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7932911 |
Processor for executing switch and translate instructions requiring wide operands
A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of...
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7934113 |
Self-clearing asynchronous interrupt edge detect latching register
A digital circuit may have at least two asynchronous clock domains with a controller responsive to a first domain clock signal and a target responsive to a second domain clock signal. A first...
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7925900 |
I/O co-processor coupled hybrid computing device
An apparatus and method provide power to perform functions on a computing device. In one example, the apparatus contains multiple processors that may operate at different power levels to consume...
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7921188 |
Computer system partitioning using data transfer routing mechanism
A computer system is described having a plurality of resources which includes a plurality of processors, a distributed point-to-point transmission infrastructure for interconnecting the plurality...
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RE42170 |
Control of information processing using one or more peripheral apparatus
At least one peripheral processing apparatus and at least one information processing apparatus, interconnected through a network, include a storage means for storing control information by which...
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7890782 |
Dynamic power management in an execution unit using pipeline wave flow control
Power is conserved by dynamically applying clocks to execution units in a pipeline of a microprocessor. A clock to an execution unit is applied only when an instruction to the execution unit is...
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7889204 |
Processor architecture for executing wide transform slice instructions
A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of...
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7877436 |
Mechanism to provide reliability through packet drop detection
A method and a data processing system for completing checkpoint processing of a distributed job with local tasks communicating with other remote tasks via a host fabric interface (HFI) and assigned...
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7844768 |
Blade server system and method of managing same
Each chassis includes a back plane having a plurality of slots and a CPU blade server and CMMs which are inserted in the slots, respectively. The back plane has a storage unit storing a housing...
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7843459 |
Processor for executing multiply matrix instructions requiring wide operands
A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of...
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7840954 |
Compilation for a SIMD RISC processor
A computer implemented method, data processing system, and computer usable code are provided for generating code to perform scalar computations on a Single-Instruction Multiple-Data (SIMD) Reduced...
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7831752 |
Method and device for interoperability in heterogeneous device environment
System, device, method, and computer program and computer program products for providing communicating between devices having similar or dissimilar characteristics and facilitating seamless...
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7827024 |
Low latency, high bandwidth data communications between compute nodes in a parallel computer
Methods, parallel computers, and computer program products are disclosed for low latency, high bandwidth data communications between compute nodes in a parallel computer. Embodiments include...
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7814252 |
Asymmetric multiprocessor
An asymmetric multiprocessor capable of increasing a degree of freedom of distributed processing, minimizing a processing load on each processor (CPU), and achieving a large reduction in power...
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7809748 |
Extended cell information in multidimensional data models
Sharable extended cell information is used by multidimensional data models to enable cell annotations and line item details. Annotations are notes stored with a cell in a multidimensional dataset....
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7805710 |
Shared code caching for program code conversion
Subject program code is translated to target code in basic block units at run-time in a process wherein translation of basic blocks is interleaved with execution of those translations. A shared...
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7802252 |
Method and apparatus for selecting the architecture level to which a processor appears to conform
A method and system for selecting the architecture level to which a processor appears to conform within a computing environment when executing specific logical partitions or programs and performing...
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7802116 |
Subsystem power management
A method according to one embodiment may include generating, by subsystem voltage regulator circuitry, a subsystem power supply for subsystem circuitry based on, at least in part, a main power...
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7797513 |
Non-blocking, multi-context pipelined processor
A packet processor whose processing capabilities are optimized by concurrently processing multiple packets within various pipelined stages. At each stage, multiple packets are processed via an...
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7779412 |
Task scheduling method for low power dissipation in a system chip
A system chip includes a plurality of processing elements for performing primary computations of a plurality of tasks, a plurality of non-processing elements for controlling flow of data associated...
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7779228 |
Quantum information processing device and method
Quantum information processing device includes resonator incorporating material containing physical systems, each of physical systems having at least four energy states, transition between two...
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7761877 |
L driving method for driving program/instruction execution, and architecture and processor thereof
The invention relates to computer architecture technology in the computer field. More specifically, the invention relates to a novel driving method for driving computer program/instruction...
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7739479 |
Method for providing physics simulation data
A method of providing physics data within a game program or simulation using a hardware-based physics processing unit having unique architecture designed to efficiently calculate physics related data.
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7725629 |
Processor array arrangement controlled by control computer
A processor arrangement having a plurality of processor units and a control computer. Each of the processor units is connected to at least one adjacent processor unit and has one control element...
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7720219 |
Apparatus and method for implementing a hash algorithm word buffer
An apparatus and method for implementing a hash algorithm word buffer. In one embodiment, a cryptographic unit may include hash logic configured to compute a hash value of a data block according to...
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