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7395538 Scalable packet processing systems and methods  
A data processing architecture includes multiple processors connected in series between a load balancer and reorder logic. The load balancer is configured to receive data and distribute the data...
7395082 Method and system for handling events in an application framework for a wireless device  
Methods and systems for application framework development for wireless devices are provided herein. Aspects of the method may include acquiring an MMI event from an MMI event queue within the MMI...
7386619 System and method for allocating communications to processors in a multiprocessor system  
In a multiprocessor-system, a system and method assigns communications to processors, processes, or subsets of types of communications to be processed by a specific processor without using a...
7383409 Cache systems and methods for employing speculative fills  
One disclosed embodiment is a multi-processor system comprising a processor having a processor pipeline that executes program instructions with data from a speculative fill that is provided in...
7376794 Coherent signal in a multi-processor system  
Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system comprising at least one data fill provided to a source processor in response to a source...
7370048 File storage method and apparatus  
A method for storing data in a data storage area of a computer that utilizes hashing functions to avoid collision of data records. A first hash function attempts to place a new data record in a...
7369683 Imaging device  
In an imaging device of the present invention, an imaging element 2 is driven in a thinning read-out mode for reading out signal charges from a subset of pixels, or in an all-pixels read-out mode...
7360217 Multi-threaded packet processing engine for stateful packet processing  
A processing engine to accomplish a multiplicity of tasks has a multiplicity of processing tribes, each tribe comprising a multiplicity of context register sets and a multiplicity of processing...
7353310 Hierarchical memory access via pipelining with deferred arbitration  
A circuit arrangement and method utilize a hierarchical pipelined memory-access structure incorporating deferred arbitration logic. A multi-stage pipelined network defines at least one pipeline...
7340565 Source request arbitration  
Multiprocessor systems and methods are disclosed. One embodiment may comprise a plurality of processor cores. A given processor core may be operative to generate a request for desired data in...
7318140 Method and apparatus for dynamic hosting partition page assignment  
A method, apparatus, and computer instructions for transferring data. The data in a first partition is received within a memory region assigned to the first partition in the logical partitioned...
7317776 Efficient pseudo-noise sequence generation for spread spectrum applications  
The invention solves the problem of efficiently generating pseudo noise sequences with an arbitrary offset delay. Novel and improved architectures are used, based on the matrix-vector pseudo noise...
7308593 Interlocked synchronous pipeline clock gating  
An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively,...
7299427 Radio prototyping system  
A method for prototyping an integrated circuit may include selecting at least one daughter card for connection to a motherboard. The daughter card is selected having an ability to provide...
7293158 Systems and methods for implementing counters in a network processor with cost effective memory  
Systems and methods for implementing counters in a network processor with cost effective memory are disclosed. Embodiments include systems and methods for implementing counters in a network...
7246222 Processor type determination based on reset vector characteristics  
A system and method of processor type determination. A reset vector from a processor is identified. Responsive to characteristics of the reset vector, a processor type of the processor is determined.
7225431 Method and apparatus for setting breakpoints when debugging integrated executables in a heterogeneous architecture  
The present invention provides inserting and deleting a breakpoint in a parallel processing system. A breakpoint is inserted in a module loaded into the execution environment of an attached...
7225319 Digital architecture for reconfigurable computing in digital signal processing  
A digital embedded architecture, includes a microcontroller and a memory device, suitable for reconfigurable computing in digital signal processing and comprising: a processor, structured to...
7197577 Autonomic input/output scheduler selector  
The automatic selection of an input/output scheduler in a computing system with a plurality of input/output schedulers is disclosed. Each of the plurality of input/output schedulers is mapped...
7174014 Method and system for performing permutations with bit permutation instructions  
The present invention provides permutation instructions usable in a programmable processor for solving permutation problems in cryptography, multimedia and other applications. PPERM and PPERM 3 R...
7155446 Performing recursive database operations  
A method and apparatus for performing recursive database operations is provided. According to one aspect, a plurality of first-stage slaves and a plurality of second-stage slaves are established in...
7146489 Methods for intelligent caching in an embedded DRAM-DSP architecture  
An efficient embedded-DRAM processor architecture and associated methods. In one exemplary embodiment, the architecture includes a DRAM array, a set of register files, set of functional units, and...
7142953 Reconfigurable digital processing system for space  
A reconfigurable digital processing system for space includes the utilization of field programmable gate arrays utilizing a hardware centric approach to reconfigure software processors in a space...
7113225 Information signal processing apparatus, picture information converting apparatus, and picture displaying apparatus  
A 525i (interlace) signal can be converted into a 1050i signal or a 525p (progressive) signal. A calculating circuit generates pixels of an output picture signal with a linear estimation expression...
7099949 Interprocess communication protocol system  
The interprocess communication protocol system provides a generic communication system for communication between specified processes in a complex digital system. In accordance with the interprocess...
7096470 Method and apparatus for implementing thread replacement for optimal performance in a two-tiered multithreading structure  
A method and apparatus are provided for implementing thread replacement for optimal performance in a two-tiered multithreading structure. A first tier thread state storage stores a limited number...
7089170 System and method for testing an embedded microprocessor system containing physical and/or simulated hardware  
A system for testing an embedded system containing a target processor executing a target program and target hardware that has a physical portion and a simulated portion. A target monitor determines...
7080238 Non-blocking, multi-context pipelined processor  
A packet processor whose processing capabilities are optimized by concurrently processing multiple packets within various pipelined stages. At each stage, multiple packets are processed via an...
7065761 Nonvolatile logical partition system data management  
A logical partition (LPAR) computer system for managing partition configuration data is disclosed, which includes a nonvolatile memory, and a plurality of logical partitions, each running...
7065682 Method for monitoring tests run on a personal computer  
The invention comprises, in various embodiments, a method for monitoring an internal test on a remote computer. The method includes reading a line from the remote computer with a processing unit....
7050826 Hardware structure for a transmission/reception device for mobile radio applications, and method for processing data in such a transmission/reception device  
A transmission/reception device for mobile radio applications has a microprocessor (DSP), at least one task-specific processor (P 1 , P 2 , P 3 ) and a processor interface ( 2 ). The task-specific...
7047392 Data processing apparatus and method for controlling staged multi-pipeline processing  
A data processing apparatus that reduces a fanout load of a control signal for controlling a pipeline includes a first pipeline processing portion for executing a processing in five divided stages,...
7043562 Irregular network  
Irregularities are provided in at least one dimension of a torus or mesh network for lower average path length and lower maximum channel load while increasing tolerance for omitted end-around...
7020854 Automated processor generation system for designing a configurable processor and method for the same  
An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set,...
7020766 Processing essential and non-essential code separately  
A conjugate processor includes an instruction set architecture (ISA) visible portion having a main pipeline, and an h-flow portion having an h-flow pipeline. The binary executed on the conjugate...
6999454 Information routing system and apparatus  
An information routing system and apparatus includes separate control and forwarding planes. The control plane is split into box management control functions and routing control functions. The box...
6996443 Reconfigurable digital processing system for space  
A reconfigurable digital processing system for space includes the utilization of field programmable gate arrays utilizing a hardware centric approach to reconfigure software processors in a space...
RE38911 Modular digital image processing via an image processing chain with modifiable parameter controls  
Aspects for allowing variably controlled alteration of image processing of digital image data in a digital image capture device include forming an image processing chain with two or more image...
6973473 Method, system and program products for managing identifiers of components of a clustered environment  
Various components are provided to manage a clustered environment. These components include a System Registry that provides a global data storage; a Configuration manager that stores data locally...
6952745 Device and method for maximizing performance on a memory interface with a variable number of channels  
The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of...
6948047 Apparatus for providing a CPU cluster via a disk I/O bus using a CPU brick which fits into a disk cavity  
A general purpose computer apparatus including a central processing unit, a main memory and a system bus. The general purpose computer apparatus further includes means for interfacing the central...
6925641 Real time DSP load management system  
A highly intelligent DSP load management system is described herein for enhancing the processing capabilities of an SOC device. The DSP load management system enables parallel processing of data at...
6920551 Configurable processor system  
A programmable integrated circuit can be designed to emulate, on demand, one of several commonly used microprocessors. It contains a configurable instruction processing unit and a superset datapath...
6918029 Method and system for executing conditional instructions using a test register address that points to a test register from which a test code is selected  
A method and system of executing computer instructions is described. Each instruction defines first and second operands and an operation to be carried out on said operands. Each instruction also...
6915409 Computerized information retrieval system  
A computerized information retrieval system having consistency among a sensory network portrayed in a visual display, a semantic network that establishes the logic of data organization and...
6907597 Method and apparatus for constructing an executable program in memory  
A method and apparatus for constructing an executable program, such as drivers in memory, obtains system configuration parameters and dynamically constructs driver code bundles from a set of code...
6883084 Reconfigurable data path processor  
A reconfigurable data path processor comprises a plurality of independent processing elements. Each of the processing elements advantageously comprising an identical architecture. Each processing...
6879954 Pattern matching for large vocabulary speech recognition systems  
A method is provided for improving pattern matching in a speech recognition system having a plurality of acoustic models. The improved method includes: receiving continuous speech input; generating...
RE38679 Data processor and method of processing data  
A second decoder ( 114 ) of an instruction decode unit ( 119 ) decodes an operation code for a multiply-add operation, and a second operation unit ( 117 ) receives two data stored in a register...
6829695 Enhanced boolean processor with parallel input  
A relational processor having multiple inputs for receiving and processing parallel words. The relational processor comprises one or more input subsections for converting parallel input data to...
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