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7603346 |
Integrated search engine devices having pipelined search and b-tree maintenance sub-engines therein
A pipelined search engine device, such as a longest prefix match (LPM) search engine device, includes a hierarchical memory and a pipelined tree maintenance engine therein. The hierarchical memory...
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7594131 |
Processing apparatus
The processing apparatus in the present invention is a processing apparatus which executes a program and performs processes of the program, and includes the following: an execution circuit having a...
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7587613 |
Method and apparatus for selectively enabling a microprocessor-based system
A system for selectively enabling a microprocessor-based system is disclosed. State information that describes the operating conditions or circumstances under which a user intends to operate the...
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7580674 |
Intelligent interface for controlling an adaptive antenna array
An antenna control interface is integrated with common integrated circuit components, such as radio transceiver or baseband modem signal processing control logic. The antenna control interface...
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7571300 |
Modular distributive arithmetic logic unit
A memory system includes a plurality of memory blocks, each having a dedicated local arithmetic logic unit (ALU). A data value having a plurality of bytes is stored such that each of the bytes is...
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7562207 |
Deterministic microcontroller with context manager
A deterministic microprocessor is disclosed in which a plurality of sets of hardware registers is provided. A corresponding plurality of hardware contexts for the microcontroller is provided by the...
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7555566 |
Massively parallel supercomputer
A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application...
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7543306 |
Method, system, and program for handling device interrupts in a multi-processor environment
Provided are a method, system, and program implemented by a device driver executing in a computer for handling interrupts from an associated device, wherein the device driver is capable of...
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7523230 |
Device and method for maximizing performance on a memory interface with a variable number of channels
The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of...
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7518120 |
Long-distance quantum communication and scalable quantum computation
Methods and apparatus for long-distance quantum communication and scalable quantum computation are disclosed. The methods and apparatus are based on probabilistic ion-photon mapping. Scalable...
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7516328 |
Contents transmission/reception scheme with function for limiting recipients
In a contents transmission/reception system, the transmission of the contents to the corresponding reception device is permitted only in the case where the device identification information...
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7512951 |
Method and apparatus for time-sliced and multi-threaded data processing in a communication system
A method for designing a time-sliced and multi-threaded architecture comprises the steps of conducting a thorough analysis of a range of applications and building a specific processor to...
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7503048 |
Scheduling synchronization of programs running as streams on multiple processors
Systems and methods for scheduling program units that are part of a process executed within an operating system are disclosed. Additionally, at least one thread is started within the operating...
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7487505 |
Multithreaded microprocessor with register allocation based on number of active threads
A mechanism in a multithreaded processor to allocate resources based on configuration information indicating how many threads are in use.
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7475001 |
Software package definition for PPU enabled system
A PPU enhanced system stores software packages implementing, at least in part, a physics subroutine. The package being implemented as a plurality of modules, at least one module being stored and...
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7472051 |
Dependable microcontroller, method for designing a dependable microcontroller and computer program product therefor
A microcontroller comprising a central processing unit and a further fault processing unit suitable for performing validation of operations of said central processing unit. The further fault...
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7457886 |
System and method for input/output scheduling
A system and method for Input/Output scheduling are described herein. In one embodiment, the method includes installing a plurality of Input/Output (I/O) schedulers to schedule I/O requests for a...
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7454542 |
System device and method for configuring and operating interoperable device having player and engine
System, device, method, and computer program and computer program products for providing communicating between devices having similar or dissimilar characteristics and facilitating seamless...
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7437542 |
Identifying and processing essential and non-essential code separately
A conjugate processor includes an instruction set architecture (ISA) visible portion having a main pipeline, and an h-flow portion having an h-flow pipeline. The binary executed on the conjugate...
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7437533 |
Quantum information processing device and method
Quantum information processing device includes resonator incorporating material containing physical systems, each of physical systems having at least four energy states, transition between two...
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7421689 |
Processor-architecture for facilitating a virtual machine monitor
Virtual-machine-monitor operation and implementation is facilitated by number of easily implemented features and extensions added to the features of a processor architecture. These features, one or...
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7409503 |
Register file systems and methods for employing speculative fills
Multi-processor systems and methods are provided. One embodiment relates to a multi-processor system that may comprise a multi-processor system with a processor having a processor pipeline that...
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7409500 |
Systems and methods for employing speculative fills
Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system with a processor having a processor pipeline that executes program instructions with data...
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7406565 |
Multi-processor systems and methods for backup for non-coherent speculative fills
Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system comprising a processor having a processor pipeline that executes program instructions with...
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7404977 |
Rennets
The present invention describes an aspartic protease produced by a fungus from the class Eurotiomycetes, comprising the amino acid sequence of FDTGSSD or FDTGSSE. The present invention further...
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7395538 |
Scalable packet processing systems and methods
A data processing architecture includes multiple processors connected in series between a load balancer and reorder logic. The load balancer is configured to receive data and distribute the data...
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7395082 |
Method and system for handling events in an application framework for a wireless device
Methods and systems for application framework development for wireless devices are provided herein. Aspects of the method may include acquiring an MMI event from an MMI event queue within the MMI...
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7386619 |
System and method for allocating communications to processors in a multiprocessor system
In a multiprocessor-system, a system and method assigns communications to processors, processes, or subsets of types of communications to be processed by a specific processor without using a...
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7383409 |
Cache systems and methods for employing speculative fills
One disclosed embodiment is a multi-processor system comprising a processor having a processor pipeline that executes program instructions with data from a speculative fill that is provided in...
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7376794 |
Coherent signal in a multi-processor system
Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system comprising at least one data fill provided to a source processor in response to a source...
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7370048 |
File storage method and apparatus
A method for storing data in a data storage area of a computer that utilizes hashing functions to avoid collision of data records. A first hash function attempts to place a new data record in a...
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7360217 |
Multi-threaded packet processing engine for stateful packet processing
A processing engine to accomplish a multiplicity of tasks has a multiplicity of processing tribes, each tribe comprising a multiplicity of context register sets and a multiplicity of processing...
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7353310 |
Hierarchical memory access via pipelining with deferred arbitration
A circuit arrangement and method utilize a hierarchical pipelined memory-access structure incorporating deferred arbitration logic. A multi-stage pipelined network defines at least one pipeline...
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7340565 |
Source request arbitration
Multiprocessor systems and methods are disclosed. One embodiment may comprise a plurality of processor cores. A given processor core may be operative to generate a request for desired data in...
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7318140 |
Method and apparatus for dynamic hosting partition page assignment
A method, apparatus, and computer instructions for transferring data. The data in a first partition is received within a memory region assigned to the first partition in the logical partitioned...
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7317776 |
Efficient pseudo-noise sequence generation for spread spectrum applications
The invention solves the problem of efficiently generating pseudo noise sequences with an arbitrary offset delay. Novel and improved architectures are used, based on the matrix-vector pseudo noise...
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7308593 |
Interlocked synchronous pipeline clock gating
An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively,...
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7299427 |
Radio prototyping system
A method for prototyping an integrated circuit may include selecting at least one daughter card for connection to a motherboard. The daughter card is selected having an ability to provide...
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7293158 |
Systems and methods for implementing counters in a network processor with cost effective memory
Systems and methods for implementing counters in a network processor with cost effective memory are disclosed. Embodiments include systems and methods for implementing counters in a network...
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7246222 |
Processor type determination based on reset vector characteristics
A system and method of processor type determination. A reset vector from a processor is identified. Responsive to characteristics of the reset vector, a processor type of the processor is determined.
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7225431 |
Method and apparatus for setting breakpoints when debugging integrated executables in a heterogeneous architecture
The present invention provides inserting and deleting a breakpoint in a parallel processing system. A breakpoint is inserted in a module loaded into the execution environment of an attached...
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7225319 |
Digital architecture for reconfigurable computing in digital signal processing
A digital embedded architecture, includes a microcontroller and a memory device, suitable for reconfigurable computing in digital signal processing and comprising: a processor, structured to...
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7197577 |
Autonomic input/output scheduler selector
The automatic selection of an input/output scheduler in a computing system with a plurality of input/output schedulers is disclosed. Each of the plurality of input/output schedulers is mapped...
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7155446 |
Performing recursive database operations
A method and apparatus for performing recursive database operations is provided. According to one aspect, a plurality of first-stage slaves and a plurality of second-stage slaves are established in...
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7146489 |
Methods for intelligent caching in an embedded DRAM-DSP architecture
An efficient embedded-DRAM processor architecture and associated methods. In one exemplary embodiment, the architecture includes a DRAM array, a set of register files, set of functional units, and...
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7142953 |
Reconfigurable digital processing system for space
A reconfigurable digital processing system for space includes the utilization of field programmable gate arrays utilizing a hardware centric approach to reconfigure software processors in a space...
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7113225 |
Information signal processing apparatus, picture information converting apparatus, and picture displaying apparatus
A 525i (interlace) signal can be converted into a 1050i signal or a 525p (progressive) signal. A calculating circuit generates pixels of an output picture signal with a linear estimation expression...
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7099949 |
Interprocess communication protocol system
The interprocess communication protocol system provides a generic communication system for communication between specified processes in a complex digital system. In accordance with the interprocess...
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7096470 |
Method and apparatus for implementing thread replacement for optimal performance in a two-tiered multithreading structure
A method and apparatus are provided for implementing thread replacement for optimal performance in a two-tiered multithreading structure. A first tier thread state storage stores a limited number...
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7089170 |
System and method for testing an embedded microprocessor system containing physical and/or simulated hardware
A system for testing an embedded system containing a target processor executing a target program and target hardware that has a physical portion and a simulated portion. A target monitor determines...
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