Matches 151 - 200 out of 343 < 1 2 3 4 5 6 7 >
Match Document Document Title
6055558 Pacing of multiple producers when information is required in natural order  
A system and method for pacing, or controlling, the processing of multiple producers when a consumer requires results from the producers in natural order. This invention regulates the use of system...
6049851 Method and apparatus for checking cache coherency in a computer architecture  
A double cache snoop mechanism in uniprocessor computer systems having a cache and coherent I/O and multiprocessor computer systems reduces the number of cycles that a processor is stalled during a...
6047347 Computer system with programmable bus size  
A computer system is presented having a mechanism for re-configuring the size of a data bus which links memory and/or input/output devices, or which links those devices to an execution unit. The...
6047371 Signal processor for performing conditional operation  
To provide a signal processor for performing processing in fewer cycles by selecting one of the two different operations in accordance with a flag signal and performing the selected operation...
6044457 State machine controller capable of producing result per clock cycle using wait/no wait and empty signals to control the advancing of data in pipeline  
A state machine controller which can be used for fetching data for a real-time computer image generation system and which provides valid data for each clock interval of a system control clock. The...
6038625 Method and system for providing a device identification mechanism within a consumer audio/video network  
A method and system for providing a device identification mechanism within a consumer electronics based audio/video network. Several consumer electronics products, e.g., television, VCR, tuner,...
6031992 Combining hardware and software to provide an improved microprocessor  
A microprocessor for a host computer designed to execute target application programs for a target computer having a target instruction set including the combination of code morphing software, and...
6029238 Control of information processing using one or more peripheral apparatus  
At least one peripheral processing apparatus and at least one information processing apparatus, interconnected through a network, include a storage means for storing control information by which...
6029239 Configuring a communications system with a configurable data transfer architecture  
A communications system utilizes an embedded Digital Signal Processor (DSP), a DSP interface and memory architecture, a micro-controller interface, a DSP operating system (OS), a data flow model,...
6023752 Digital data apparatus for transferring data between NTDS and bus topology data buses  
A program driver means is disclosed that allows for the exchange of inforion between a NTDS device and a device having a bus topology, especially a VMEbus. The program driver utilizes chain...
6023751 Computer system and method for evaluating predicates and Boolean expressions  
A computer system provides fast evaluation of predicates and Boolean expressions with a set of operations for determining a value in a specified register from a plurality of inputs. The execution...
6016539 Datapath control logic for processors having instruction set architectures implemented with hierarchically organized primitive operations  
A new datapath control logic for processors with ISA implemented employing hierarchically organized primitive operations is disclosed. The new datapath control logic includes a primary control unit...
6009453 Multi-program execution controlling apparatus and method  
A storage section stores a plurality of programs. A central processing section controls execution of each of the plurality of programs stored in the storage section. A setting section, in...
6006298 On-line module replacement system  
In an electronic apparatus having a plurality of printed boards or modules, an on-line module replacement system for allowing the desired of the boards to be inserted or removed while maintaining...
6006318 General purpose, dynamic partitioning, programmable media processor  
A general purpose, programmable media processor for processing and transmitting a media data stream of audio, video, radio, graphics, encryption, authentication, and networking information in...
6003120 Method and apparatus for performing variable length processor write cycles  
A computer system comprising a processor, a memory subsystem having a fast memory and a slow memory, and other at least one peripheral-performing variable length processor write cycles is...
6000016 Multiported bypass cache in a bypass network  
A microprocessor includes a register file that contains registers for storing pieces of data for use by execution units that receive the pieces of data through source ports. A bypass cache includes...
5999734 Compiler-oriented apparatus for parallel compilation, simulation and execution of computer programs and hardware models  
A distributed, compiler-oriented database is disclosed with operating modes including parallel compilation, parallel simulation and parallel execution of computer programs and hardware models. The...
5996056 Apparatus for reducing a computational result to the range boundaries of a signed 8-bit integer in case of overflow  
An intermediate result signal arising from a manipulation of data signals is checked and reduced without using conditional branches, thereby improving instruction processing. Data signals are...
5991864 Power connectors, antenna connectors and telephone line connectors for computer devices utilizing ra  
A computer apparatus for receiving a removable communication card such as a radio card or a modem card. A radio or modem is self-contained inside a housing of the communication card and has an...
5987585 One-chip microprocessor with error detection on the chip  
A one-chip microprocessor, in which a built-in cache memory unit 20 has parities, and a cache parity generating & checking unit 21 checks parity of data read from the built-in cache memory unit 20,...
5983321 Cache holding register for receiving instruction packets and for providing the instruction packets to a predecode unit and instruction cache  
An instruction cache employing a cache holding register is provided. When a cache line of instruction bytes is fetched from main memory, the instruction bytes are temporarily stored into the cache...
5983323 Processor node  
A processor node which includes at least one local bus (10) that assures a parallel link among the processors (8), a local memory (11) and a shared cache (12), and one network bus (13) that assures...
5983339 Power down system and method for pipelined logic functions  
Logic circuitry added to each stage of a pipeline of staged logic circuitry sequentially removes a clock signal from each stage when data incoming to the pipeline is invalid, or not to be processed...
5983336 Method and apparatus for packing and unpacking wide instruction word using pointers and masks to shift word syllables to designated execution units groups  
An unpacking circuit and operating method in a very long instruction word (VLIW) processor provides for parallel handling of a packed wide instruction in which a packed wide instruction is divided...
5978822 Circuit for rotating, left shifting, or right shifting bits  
A circuit having a single branch, which is controllable to implement either a left or right shift of bits of a data word. Preferably, the circuit is controllable to implement any selected one of...
5978897 Sequence operation processor employing multi-port RAMs for simultaneously reading and writing  
A sequence operation processor and a sequence operation processing method for processing sequence operations at high speed using a multi-port RAM. The sequence operation processor reads data from...
5978592 Video decompression and decoding system utilizing control and data tokens  
A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over...
5968155 Digital gate computer bus  
A computer bus includes a set of computer bus input nodes to receive a set of computer bus input signals generated by system cards attached to the computer bus. The computer bus input signals are...
5970254 Integrated processor and programmable data path chip for reconfigurable computing  
A reconfigurable processor chip has a mixture of reconfigurable arithmetic cells and logic cells for higher effective utilization than a standard FPGA. The reconfigurable processor includes a...
5970064 Real time control architecture for admission control in communications network  
A communications network comprising N node elements operates N decision tables for controlling admission and control of data communications to the N node elements (FIG. 2). The performance of the...
5966544 Data speculatable processor having reply architecture  
A microprocessor having a replay architecture with an execution core for performing data speculation in executing an instruction, a delay unit for making a copy of the instruction and holding the...
5961575 Microprocessor having combined shift and rotate circuit  
Circuit for performing arithmetic operations in a 32-bit architecture. The circuit includes a five stage shift and rotate circuit coupled between first and second 32-bit busses in the following...
5958021 Input-output interface circuit with multiplexers selecting an external signal or an internal output signal as the input signal from an I/O terminal  
An input-output interface circuit operative in three different modes which utilizes a first signal selector, operative selectively in an external signal output mode and an internal signal...
5960210 Nested-loop-specialized circuitry for repeatedly performed arithmetic operations in digital signal processor and method thereof  
An improved apparatus for processing a repeatedly performed arithmetic operation for a digital signal processor and a method thereof which are capable of pushing and popping values related to a...
5958038 Computer processor with two addressable memories and two stream registers and method of data streaming of ALU operation  
A processor having a modified Harvard architecture having first and second memories, an address register file divided into first and second sets of registers, first and second stream registers, and...
5960209 Scaleable digital signal processor with parallel architecture  
A distributed architecture parallel processing apparatus, includes a central microprocessor having at least one external interface connected to a similar interface of a neighboring parallel...
5956520 Microcomputer for accessing a memory outside the chip by using an address generated from the CPU  
An external bus I/F section has a function in which, when a bus access is requested by an instruction execution section, high-order several bits of a logical address generated by a CPU are...
5956262 Digital filtering device  
A digital sample filtering device comprising storage device including ROM and RAM memory for storing in an interlaced manner, coefficients of at least two filters along with for each coefficient,...
5956517 Data driven information processor  
A data driven information processor includes an operation processor unit for prestoring a data flow program and carrying out processing, and a storage microprocessor unit having a plurality of data...
5953537 Method and apparatus for reducing the number of programmable architecture elements required for implementing a look-up table in a programmable logic device  
A method and apparatus for reducing the number of programmable architecture elements required for implementing a look-up table in a programmable logic device. At least one logic function to be...
5948098 Execution unit and method for executing performance critical and non-performance critical arithmetic instructions in separate pipelines  
A CPU (central processing unit) of a computer that comprises an issue unit and an execution unit. The issue unit selectively issues arithmetic instructions of a predefined arithmetic instruction...
5944811 Superscalar processor with parallel issue and execution device having forward map of operand and instruction dependencies  
In a superscalar processor for fetching a prescribed peak number of instructions in parallel in each period until such instructions are fetched to a predetermined peak number, such as ten, an...
5941966 Method and apparatus using a plural level processor for controlling a data bus  
The invention relates to a device and a process for the control of a data transmission channel or data bus, in particular a data bus on which the data is transmitted in a bit serial fashion...
5935230 Multiprocessor arrangement including bus arbitration scheme involving plural CPU clusters that address each other as "phantom" CPUs  
At least two clusters of CPUs are present in a multiprocessor computer system. Each CPU cluster has a given number of CPUs, each CPU having an associated ID such as an ID number. An additional ID...
5931930 Processor that indicates system bus ownership in an upgradable multiprocessor computer system  
A computer system is disclosed having a processor with a type input pin that indicates whether the processor is coupled as an OEM processor a single processor or a dual processor computer system or...
5933642 Compiling system and method for reconfigurable computing  
A compiling system and method for generating a sequence of program instructions for use in a dynamically reconfigurable processing unit having an internal hardware organization that is selectively...
5930518 Arithmetic unit  
An arithmetic unit performs a demodulating operation for a received signal, a synchronizing operation based on a demodulated signal, a voice decoding operation for the demodulated signal, a voice...
5930483 Method and apparatus for communications control on a small computer system interface  
A method and apparatus are provided for controlling communications on a small computer system interface (SCSI). A cache memory is arranged for storing an input queue, a status queue and a cache...
5923890 Method and apparatus for optimizing the handling of synchronous requests to a coupling facility in a sysplex configuration  
A method and apparatus for optimizing the handling of a synchronous request issued from a system partition of a logically partitioned machine to a selected coupling facility. The coupling facility...
Matches 151 - 200 out of 343 < 1 2 3 4 5 6 7 >