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7617367 |
Memory system including a two-on-one link memory subsystem interconnection
A memory system including a first memory subsystem having a buffer device with a first port and a second port, one or more memory devices coupled to the buffer device via the second port, and a...
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7617356 |
Refresh port for a dynamic memory
A refresh port for a dynamic memory. In one embodiment, an apparatus includes a memory and a refresh command interface to receive a refresh command including a portion indicating signal. Refresh...
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7617350 |
Carrier having daisy chained memory chips
A carrier having at least one memory chip in a daisy chain of memory chips. A first carrier has at least a portion of an entire daisy chain of memory chips attached to the first carrier. An...
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7613866 |
Method for controlling access to a multibank memory
The present invention relates to a method for scheduling and controlling access to a multibank memory having at least two banks, and to an apparatus for reading from and/or writing to recording...
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7609562 |
Configurable device ID in non-volatile memory
Various embodiments of the invention may use one or more programmable non-volatile registers in each memory device to provide a separate device address for that device. These registers may be...
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7594088 |
System and method for an asynchronous data buffer having buffer write and read pointers
A system and method for facilitating the adjustment of timing parameters between a memory controller operating in a first clock domain and a memory device operating in a second clock domain. A...
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7587559 |
Systems and methods for memory module power management
Systems and methods for determining memory module power requirements in a memory system. Embodiments include a memory system with a physical memory and a memory controller. The physical memory...
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7587545 |
Shared memory device
A shared memory device able to simplify interconnects up to memories, able to prevent a reduction of performance due to an increase of area and longer interconnects, and able to speed up memory...
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7587515 |
Method and system for restrictive caching of user-specific fragments limited to a fragment cache closest to a user
A method, a system, an apparatus, and a computer program product are presented for a fragment caching methodology. Within the request path from a client to a server, a first computing device may...
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7584336 |
Systems and methods for providing data modification operations in memory subsystems
Systems and methods for providing data modification operations in memory subsystems. Systems include a plurality of memory devices, a memory controller, one or more memory busses connected to the...
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7584321 |
Memory address and datapath multiplexing
Circuits, methods, and apparatus for multiplexing addresses and data at a memory interface such that multiple data widths are provided without the need to change a motherboard or other printed...
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7581073 |
Systems and methods for providing distributed autonomous power management in a memory system
Systems and methods for providing distributed autonomous power management in a memory system. Embodiments include a memory system for storing and retrieving data for a processing system. The memory...
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7580997 |
State recovery
A method of recovering the state of a system, which system comprises at least one counter, which counter represents an instantaneous state of an entity in a system. The counter will increase in...
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7577760 |
Memory systems, modules, controllers and methods using dedicated data and control busses
A memory system includes a plurality of memory devices arranged in sets on at least one memory module, each set including at least one memory device. In some embodiments, the system further...
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7574573 |
Reactive placement controller for interfacing with banked memory storage
An invention is provided for a reactive placement controller for interfacing with a banked memory storage. The reactive placement controller includes a read/write module, which is coupled to a...
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7571274 |
Method and system for virtual enclosure management
A process and system for virtually managing enclosures. A process determines whether a system includes an enclosure processor, a virtual enclosure processor, or both an enclosure processor and a...
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7565343 |
Search apparatus and search management method for fixed-length data
Fixed-length data ( 560 ) contained in a database ( 560 ) are segmented into a number of pieces of data that are searchable at a time and searching is performed at high speed. As means for it, a...
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7564727 |
Apparatus and method for configurable power management
A method and apparatus to facilitate low-power consumption through a configurable suspend mode of operation of a PLD, the PLD comprising an application logic block coupled to receive configuration...
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7562202 |
Systems, methods, computer readable medium and apparatus for memory management using NVRAM
A system and method is disclosed for improving data integrity and the efficiency of data storage in separate memories of a computing device. In particular, the present invention introduces a...
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7562184 |
DRAM controller for graphics processing operable to enable/disable burst transfer
An interface unit 20 assigns different SDRAMs 1 and 2 to adjacent drawing blocks in a frame-buffer area. In processing that extends across the adjacent drawing blocks, active commands, for...
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7562178 |
Memory hub and method for memory sequencing
A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics—for example, page hit...
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7558934 |
Data storage unit, data storage controlling apparatus and method, and data storage controlling program
A data storage unit is provided in which all data are stored into a memory including a plurality of memory banks and a plurality of desired data is read simultaneously, without any load to the...
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7558933 |
Synchronous dynamic random access memory interface and method
A memory interface allows access SDRAM by receiving a column address for a data read or write of a burst of data units. Each data unit in the burst has an expected bit size. The interface generates...
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7558908 |
Structure of sequencers that perform initial and periodic calibrations in a memory system
A structure of sequencers, a method, and a computer program are provided for performing initial and periodic calibrations in an XDR™ memory system. A memory controller that performs these...
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7549013 |
Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices
In one embodiment of the present invention, a memory storage system for storing information organized in sectors within a nonvolatile memory bank is disclosed. The memory bank is defined by sector...
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7546451 |
Continuously providing instructions to a programmable device
A system and method for enabling a programmable device to execute instructions without interruption. An instruction space for storing instructions from a host application is bifurcated to define a...
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7546424 |
Embedded processor with dual-port SRAM for programmable logic
Methods and apparatus for programmable logic devices including embedded processors having a dual-port SRAMs. A programmable logic integrated circuit includes a programmable logic portion having a...
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7546386 |
Method for virtual resource initialization on a physical adapter that supports virtual resources
A method for directly sharing a network stack offload I/O adapter that directly supports resource virtualization and does not require a LPAR manager or other intermediary to be invoked on every I/O...
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7545664 |
Memory system having self timed daisy chained memory chips
A memory system having a memory controller and a memory. The memory comprises one or more daisy chains of self timed memory chips. An address/command word is chained through a daisy chain of memory...
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7543106 |
Apparatus and method for controlling refresh of semiconductor memory device according to positional information of memory chips
A memory controller controlling a plurality of semiconductor memory devices includes a refresh control circuit controlling refresh operations of the semiconductor memory devices according to...
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7543102 |
System and method for performing multi-rank command scheduling in DDR SDRAM memory systems
A DRAM command scheduling algorithm is presented that is designed to alleviate various constraints imposed upon high performance, high datarate, short channel DDRx SDRAM memory systems. The...
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7539842 |
Computer memory system for selecting memory buses according to physical memory organization information stored in virtual address translation tables
Systems and methods for program directed memory access patterns including a memory system with a memory, a memory controller and a virtual memory management system. The memory includes a plurality...
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7539811 |
Scaleable memory systems using third dimension memory
A non-volatile scalable memory circuit is described, including a bus formed on a substrate that includes active circuitry, metallization layers, and a plurality of high density third dimension...
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7536519 |
Memory access control apparatus and method for accomodating effects of signal delays caused by load
A memory controller determines a load level based on the number of connected memory devices informed by a switch or the like. If it is determined that the load level is high, the memory controller...
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7536499 |
Memory access control device and processing system having same
A memory access control device enabling freer access from a plurality of ports to a plurality of memories and a processing system having the same are provided. From among addresses generated at a...
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7533213 |
Memory hub and method for memory system performance monitoring
A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics—for example, page hit...
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7533212 |
System memory board subsystem using DRAM with integrated high speed point to point links
A memory system comprising memory modules including memory chips including integrated switching circuits. A memory controller coupled to the memory modules is configured to initiate memory...
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7526597 |
Buffered memory having a control bus and dedicated data lines
A memory system architecture/interconnect topology includes a configurable width buffered module having a configurable width buffer device. The configurable width buffer device is coupled to at...
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7526596 |
***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***
Methods and systems for an identifier-based memory section
A storage system that may include one or more memory devices, a memory interface device corresponding to one or more of the memory devices, which are organized in sections, and a section...
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7523248 |
System having a controller device, a buffer device and a plurality of memory devices
A system comprises a controller device, an integrated circuit buffer device and a first and second memory device. A first plurality of signal lines is coupled to the controller device. A second...
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7523230 |
Device and method for maximizing performance on a memory interface with a variable number of channels
The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of...
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7519788 |
System and method for an asynchronous data buffer having buffer write and read pointers
A system and method for facilitating the adjustment of timing parameters between a memory controller operating in a first clock domain and a memory device operating in a second clock domain. A...
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7519762 |
Method and apparatus for selective DRAM precharge
Apparatus and method for using a precharge command in which a plurality of address lines are individually used to specify which banks of memory cells within a memory device have an open row that is...
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7519696 |
Method and apparatus for dynamically modifying a computer system configuration
One embodiment is directed to a method and apparatus for modifying a configuration of a computer system including a host computer and at least one computer system resource accessible to at least...
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7516282 |
Control device and control method for memory
A control device for a memory is provided. The control device includes a micro-control unit (MCU), a command queue, a command sequencer, and a table. The control device is coupled to the memory and...
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7516264 |
Programmable bank/timer address folding in memory devices
A set of N copies of bank control logic are provided for tracking the banks within the memory modules (DRAMS). When the total number of banks within the memory module(s) is greater than N, the...
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7512847 |
Method for estimating and reporting the life expectancy of flash-disk memory
A method for managing a memory device, a memory device so managed and a system that includes such a memory device. A value of a longevity parameter of the device is monitored after a data operation...
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7509302 |
Device, method and program for providing a high-performance storage access environment while issuing a volume access request including an address of a volume to access
The present invention provides a high-performance storage access environment to a user who moves around a wide area, while increasing the fault resistance of the system. A plurality of network...
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7508706 |
Nonvolatile semiconductor memory device provided with data register for temporarily holding data in memory array
A precharge signal generation circuit outputs a precharge signal including a pulse every access cycle with respect to a data register in a first mode, and generates a precharge signal by masking...
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7506130 |
Mirrored computer memory on split bus
A fully mirrored memory system includes at least one split memory bus, with each portion of the split memory bus having active memory and mirror memory. Each portion of the memory bus transfers a...
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