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9037774 Memory module with load reducing circuit and method of operation  
A memory module includes a plurality of memory devices and is operable in a computer system to perform memory operations in response to memory commands from a memory controller of the computer...
9032167 Write operations to and from multiple buffers  
Computer readable media, methods and apparatuses are disclosed that may be configured for sequentially reading data of a file stored on a storage medium. The disclosure also provides for...
9026714 Memory expansion using rank aggregation  
In one embodiment, a method includes receiving from a memory controller, a request to access memory stored at memory modules, the request directed to one of a plurality of logical ranks, mapping...
9026721 Managing defective areas of memory  
Methods of operating a memory, and memories for performing such methods, include determining that a particular area of the memory is defective, locating a free area of the memory, programming data...
9021176 Memory device and method with on-board cache system for facilitating interface with multiple processors, and computer system using same  
A memory device includes an on-board cache system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The cache...
9015399 Multiple data channel memory module architecture  
The present invention is directed generally to systems and methods which provide a memory module having multiple data channels that are independently accessible (i.e., a multi-data channel memory...
9009400 Semiconductor memory systems with on-die data buffering  
A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an...
9009383 Memory controller mapping on-the-fly  
Systems, methods, and devices for dynamically mapping and remapping memory when a portion of memory is activated or deactivated are provided. In accordance with an embodiment, an electronic device...
9003163 Combining a remote TLB lookup and a subsequent cache miss into a single coherence operation  
The disclosed embodiments provide techniques for reducing address-translation latency and the serialization latency of combined TLB and data cache misses in a coherent shared-memory system. For...
8996782 Memory system and bank interleaving method  
According to embodiments, a memory system includes a plurality of memory chips configuring banks, an instruction generator, and a memory controller. The instruction generator generates a plurality...
8990489 Multi-rank memory module that emulates a memory module having a different number of ranks  
A transparent four rank memory module has a front side and a back side. The front side has a third memory rank stacked on a first memory rank. The back side has a fourth memory rank stacked on a...
8990473 Managing requests to open and closed banks in a memory system  
Systems and methods are provided that facilitate memory storage in a memory device. The system contains a memory controller and a memory array communicatively coupled to the memory controller. The...
8990491 Eye scan for asymmetric shaped communication signal  
Techniques for processing signal information from a high speed communication bus. The techniques includes determining spatial regions on an eye characterized by a start point, an end point, a...
8977822 Memory device and method having on-board processing logic for facilitating interface with multiple processors, and computer system using same  
A memory device includes an on-board processing system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The...
8977813 Implementing RAID in solid state memory  
The present disclosure includes systems and techniques relating to implementing fault tolerant data storage in solid state memory. In some implementations, a method includes receiving a data...
8977801 Computing system utilizing dispersed storage  
A computing system comprises at least a processing module, a main memory, a memory controller, and a plurality of memory components. A method begins by the memory controller receiving a memory...
8977800 Multi-port cache memory apparatus and method  
Provided is a multi-port cache memory apparatus and a method of the multi-port cache memory apparatus. The multi-port memory apparatus may divide an address space into address regions and allocate...
8966208 Semiconductor memory device with plural memory die and controller die  
A semiconductor memory device including a plurality of memory die and a controller die. The controller die is connected to an internal control bus. The controller die is configured to provide to a...
8966153 Semiconductor memory device and information data processing apparatus including the same  
A semiconductor memory device includes a plural number of data input/output pins, a plural number of banks, in each of which a plural number of the information data is stored, a selector and a...
8966152 On-chip memory (OCM) physical bank parallelism  
According to an example embodiment, a processor is provided including an integrated on-chip memory device component. The on-chip memory device component includes a plurality of memory banks, and...
8959297 Retrieving a user data set from multiple memories  
An apparatus and associated methodology for a data storage system having a data storage space operably transferring user data via input/output (I/O) commands between the data storage system and...
8959308 Device and method for monitoring and using internal signals in a programmable system  
The invention relates to a device for monitoring and using internal signals in a programmable system (2), wherein said device includes at least one programmable system (2) including at least one...
8954687 Memory hub and access method having a sequencer and internal row caching  
A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices. The memory hub includes a row cache memory...
8954644 Apparatus and method for controlling memory  
Disclosed herein are an apparatus and method for controlling memory. The apparatus includes a memory access request buffer unit, a memory access request control unit, and a bank control unit. The...
8954700 Method and apparatus for managing processing thread migration between clusters within a processor  
A method, and corresponding apparatus, of managing processing thread migrations within a plurality of memory clusters, includes embedding, in memory components of the plurality of memory clusters,...
8949504 Memory devices and memory control methods with ISP code  
A memory device is provided, including a first memory die, a second memory die and a controller. The first memory die has a first system block. The second memory die has a second system block. The...
8943294 Software architecture for service of collective memory and method for providing service of collective memory using the same  
Disclosed is a software architecture supporting a large-capacity collective memory layer in a multi-node system by using a remote direct memory access technique and a software virtualization...
8930597 Method and apparatus for supporting low-latency external memory interfaces for integrated circuits  
An external memory interface includes an input/output (IO) logic unit operable to convert a rate of data from a first rate corresponding to a memory controller/schedule unit to a second rate...
8930616 System refresh in cache memory  
System refresh in a cache memory that includes generating a refresh time period (RTIM) pulse at a centralized refresh controller of the cache memory and activating a refresh request at the...
8923405 Memory access ordering for a transformation  
An apparatus generally having a plurality of memories and a first circuit is disclosed. The memories may be configured to store a plurality of first data points. The first data points generally...
8924623 Method for managing multi-layered data structures in a pipelined memory architecture  
A method for managing multi-layered data structures in a pipelined memory architecture, comprising the steps of: —providing a multi-level data structure where each level corresponds to a memory...
8924660 Split-word memory  
Method, process, and apparatus to efficiently store, read, and/or process portions of word data. A portion of a data word, which includes multiple portions, may be read by a computer processor....
8918589 Memory controller, memory system, semiconductor integrated circuit, and memory control method  
A memory controller (101) according to this invention includes: a command generation unit (102) which generates access commands each including a physical address, based on an access request...
8918613 Storage apparatus and data management method for storage area allocation based on access frequency  
Provided are a storage apparatus and data management method with which the usage ratio of each of the storage tiers is determined beforehand for each virtual volume and data can be managed by...
8914592 Data storage apparatus with nonvolatile memories and method for controlling nonvolatile memories  
According to one embodiment, a data storage apparatus includes a write command module, a read command module, and a controller. The write command module is configured to process a write command...
8908466 Multi-column addressing mode memory system including an integrated circuit memory device  
A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit...
8904096 Storage device and information processing system  
A storage device able to make a redundant write operation of unselected data unnecessary and able to optimize an arrangement of pages to a state having a high efficiency for rewriting, wherein the...
8898368 Redriven/retimed registered dual inline memory module  
A memory module may include a plurality of dynamic random access memory (DRAM) chips, each of which may have one or more data input/output (D/Q) terminals. The memory module may include data...
8892844 Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers  
Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers are described. In one such method, where memory cells are divided into at least a first...
8886898 Efficient interleaving between a non-power-of-two number of entities  
Some embodiments of the present invention provide a system that maps an address to an entity, wherein the mapping interleaves addresses between a number of entities. During operation, the system...
8880772 System and method for serial interface topologies  
A system and method for serial interface topologies is disclosed. A serial interface topology includes a replication device configured to receive control information from a controller interface....
8874808 Hierarchical buffer system enabling precise data delivery through an asynchronous boundary  
The present invention provides a system and method for controlling data entries in a hierarchical buffer system. The system includes an integrated circuit device with a memory core, a high speed...
8874822 Scheduling access requests for a multi-bank low-latency random read memory device  
Described herein are method and apparatus for scheduling access requests for a multi-bank low-latency random read memory (LLRRM) device within a storage system. The LLRRM device comprising a...
8874843 Systems with programmable heterogeneous memory controllers for main memory  
A translating memory module is disclosed including a printed circuit board, at least one memory integrated circuit coupled to the printed board, and at least one support chip coupled to the...
8874825 Storage device and method using parameters based on physical memory block location  
A data storage device and methods of performing memory operations using location-based parameters are disclosed. A method includes identifying a set of parameter values associated with a physical...
8874809 Assembly and a method of receiving and storing data while saving bandwidth by controlling updating of fill levels of queues  
An assembly where a number of receivers receiving packets for storing in queues in a storage and a means for de-queuing data from the storage. A controller determines addresses for the storage,...
8868823 Data storage apparatus and method of calibrating memory  
According to one embodiment, a data storage apparatus includes an interface module and a controller. The interface module is configured to control rewritable nonvolatile memories provided for the...
8868826 Facilitating communication between memory devices and CPUs  
According to one embodiment, an apparatus comprises one or more memory devices and one or more processors coupled to a circuit board. The memory devices are configured according to a second memory...
8850115 Memory package utilizing at least two types of memories  
A memory package and methods for writing data to and reading data from the memory package are presented. The memory package includes a volatile memory and a high-density memory. Data is written to...
8850101 System and method to reduce memory access latencies using selective replication across multiple memory ports  
In one embodiment, a system comprises a plurality of memory ports. The memory ports are distributed into a plurality of subsets, where each subset is identified by a subset index. The system...