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7716392 Computer system having an I/O module directly connected to a main storage for DMA transfer  
A computer system includes a CPU (Central Processing Unit) and a main storage interconnected by a bus to the CPU. The I/O module for transferring received data and data to be transmitted to and...
7707355 Memory system for selectively transmitting command and address signals  
A system includes a memory controller adapted to output address signals, command signals and select signals; a plurality of memory modules; and a plurality of buses each corresponding to one of...
7707363 Multi-port memory architecture for storing multi-dimensional arrays II  
An N-port memory architecture is disclosed that stores multi-dimensional arrays so that: (1) N contiguous elements in a row can be accessed without blocking, (2) N contiguous elements in a column...
7707388 Computer memory architecture for hybrid serial and parallel computing systems  
In one embodiment, a serial processor is configured to execute software instructions in a software program in serial. A serial memory is configured to store data for use by the serial processor in...
7707351 Methods and systems for an identifier-based memory section  
A storage system that may include one or more memory devices, a memory interface device corresponding to one or more of the memory devices, which are organized in sections, and a section...
7707366 Memory control device  
Improved efficiency of address/data communication over a memory bus. A memory-control device is located between a processor 30 and memory ranks 40a, 40b and controls access to the memory ranks...
7702883 Variable-width memory  
A variable-width memory may comprise multiple memory banks from which data may be selectively read in such a way that overall memory access requirements may be reduced, which may result in...
7702880 Hybrid mapping implementation within a non-volatile memory system  
Methods and apparatus for allowing different mapping implementations, including a many-to-one logical to physical block mapping, to be used within a memory system are disclosed. According to one...
7702834 Data transmission method serial bus system and switch-on unit for a passive station  
In a serial bus system data in the form of telegrams, representing process images of control tasks of the active station, are transmitted to the connected passive stations, and the process data...
7697363 Memory device having data input and output ports and memory module and memory system including the same  
A memory device is adapted to be connected in a daisy chain with a memory controller and one or more other memory devices. The memory device includes at least one data input port and at least one...
7694193 Systems and methods for implementing a stride value for accessing memory  
Systems and methods for implementing a stride value for memory are provided. One embodiment includes a system comprising a plurality of memory modules configured to store interleaved data in a...
7694109 Data processing apparatus of high speed process using memory of low speed and low power consumption  
When fetching an instruction from a plurality of memory banks, a first pipeline cycle corresponding to selection of a memory bank and a second pipeline cycle corresponding to instruction readout...
7694093 Memory module and method for mirroring data by rank  
A memory module including first and second ranks is provided. Each rank includes a separate plurality of individually accessible memory locations. Also included in the memory module is a control...
7689981 Mobile handset with efficient interruption point detection during a multiple-pass update process  
A mobile handset with a fault tolerant update agent employs an efficient interruption point detection technique to recover from interruptions during the update of firmware or software. In one...
7685354 Multiple-core processor with flexible mapping of processor cores to cache banks  
A multiple-core processor providing flexible mapping of processor cores to cache banks. In one embodiment, a processor may include a cache including a number of cache banks. The processor may...
7681023 Method for ensuring optimal memory configuration in a computer  
A method according to the invention ensures optimal memory configuration in a computer: A determination is made whether performance can be improved by rearranging the DIMMs that are installed in...
7673093 Computer system having daisy chained memory chips  
A computer system having a memory system having a memory controller and a memory. The memory controller is coupled to a processor and to the memory. The memory comprises one or more daisy chains...
7673094 Memory devices with buffered command address bus  
Circuits and methods are provided that alleviate overloading of the command address bus and limit decreases in command address bus bandwidth to allow increased numbers of memory modules to be...
7673103 Logging of level-two cache transactions into banks of the level-two cache stores the transactions for diagnostic and debug  
A plurality of processor cores on a chip is operated in a normal fashion in a debug and diagnostic mode of operation of the processor. A crossbar switch on the chip couples and decouples the...
7664922 Data transfer arbitration apparatus and data transfer arbitration method  
When a concentration of access requests on a specific bank occurs, the delay time is caused due to the competition among the accesses, thereby lowering the processing speed of an information...
7664905 Page stream sorter for poor locality access patterns  
In some applications, such as video motion compression processing for example, a request pattern or “stream” of requests for accesses to memory (e.g., DRAM) may have, over a large number of...
7660951 Atomic read/write support in a multi-module memory configuration  
Efficient transfer of data to and from random access memory is described. Multiple request sources and a memory system comprise memory modules having memory banks, each bank containing rows of...
7660940 Carrier having daisy chain of self timed memory chips  
A carrier having at least one self timed memory chip in a daisy chain of memory chips. A first carrier has at least a portion of a daisy chain of memory chips attached to the first carrier. An...
7653448 NICAM processing method  
A NICAM processing method includes receiving and temporarily storing a current frame of A-channel and B-channel input data into a first memory at a first clock rate. Companded A-channel and...
7650457 Memory module comprising a plurality of memory devices  
A memory module stores data in the form of code words, each code word comprising useful bits and check bits for error correction. The memory module contains a first group of the memory devices...
7647470 Memory device and controlling method for elongating the life of nonvolatile memory  
A memory device and controlling method for nonvolatile memory are provided. The memory device and the controlling method for a nonvolatile memory are provided by which, where a file management...
7640386 Systems and methods for providing memory modules with multiple hub devices  
Systems and methods for providing memory modules with multiple hub devices. Exemplary systems include a cascade-interconnect memory system with a memory bus, a memory controller and a memory...
7640366 Storage controller to control access to storage device via serial communication unit by executing control step units  
A storage controller includes a CPU for controlling each component in the storage controller; a ROM for storing programs executed by the CPU and data required for this execution; a RAM employed as...
7636833 Method for selecting memory busses according to physical memory organization information associated with virtual address translation tables  
Systems and methods for program directed memory access patterns including a memory system with a memory, a memory controller and a virtual memory management system. The memory includes a plurality...
7636808 Semiconductor device  
A semiconductor device employs a SESO memory or a phase change memory which has a smaller memory cell area than SRAM. The semiconductor device has a plurality of memory banks each composed of the...
7631152 Determining memory flush states for selective heterogeneous memory flushes  
A memory flush is processed in accordance with a state machine that keeps track of the flush states of a memory target. A memory target is not flushed if it has not been written to, or if a memory...
7631138 Adaptive mode switching of flash memory address mapping based on host usage characteristics  
In a non-volatile memory storage system such as a flash EEPROM system, a controller switches the manner in which data sectors are mapped into blocks and metablocks of the memory in response to...
7627712 Method and system for managing multi-plane memory devices  
A computational system comprising a controller and a multi-plane solid state memory device accessible to the controller is disclosed. The controller is configured to provide access to a virtual...
7627711 Memory controller for daisy chained memory chips  
A memory controller configured to control a daisy chain of memory chips. The memory controller receives read and write requests from a processor, determines a daisy chain of memory chips that the...
7624310 System and method for initializing a memory system, and memory device and processor-based system using same  
Systems, controllers and methods are disclosed, such as an initialization system including a controller that receives patterns of read data coupled from a memory device through a plurality of read...
7620793 Mapping memory partitions to virtual memory pages  
Systems and methods for addressing memory using non-power-of-two virtual memory page sizes improve graphics memory bandwidth by distributing graphics data for efficient access during rendering....
7620784 High speed nonvolatile memory device using parallel writing among a plurality of interfaces  
Described is a high speed nonvolatile memory device and technology that includes a controller coupled via interfaces to sets of nonvolatile storage, such as separate flash memory chips or separate...
7617367 Memory system including a two-on-one link memory subsystem interconnection  
A memory system including a first memory subsystem having a buffer device with a first port and a second port, one or more memory devices coupled to the buffer device via the second port, and a...
7617356 Refresh port for a dynamic memory  
A refresh port for a dynamic memory. In one embodiment, an apparatus includes a memory and a refresh command interface to receive a refresh command including a portion indicating signal. Refresh...
7617350 Carrier having daisy chained memory chips  
A carrier having at least one memory chip in a daisy chain of memory chips. A first carrier has at least a portion of an entire daisy chain of memory chips attached to the first carrier. An...
7613866 Method for controlling access to a multibank memory  
The present invention relates to a method for scheduling and controlling access to a multibank memory having at least two banks, and to an apparatus for reading from and/or writing to recording...
7609562 Configurable device ID in non-volatile memory  
Various embodiments of the invention may use one or more programmable non-volatile registers in each memory device to provide a separate device address for that device. These registers may be...
7594088 System and method for an asynchronous data buffer having buffer write and read pointers  
A system and method for facilitating the adjustment of timing parameters between a memory controller operating in a first clock domain and a memory device operating in a second clock domain. A...
7587545 Shared memory device  
A shared memory device able to simplify interconnects up to memories, able to prevent a reduction of performance due to an increase of area and longer interconnects, and able to speed up memory...
7587515 Method and system for restrictive caching of user-specific fragments limited to a fragment cache closest to a user  
A method, a system, an apparatus, and a computer program product are presented for a fragment caching methodology. Within the request path from a client to a server, a first computing device may...
7587559 Systems and methods for memory module power management  
Systems and methods for determining memory module power requirements in a memory system. Embodiments include a memory system with a physical memory and a memory controller. The physical memory...
7584321 Memory address and datapath multiplexing  
Circuits, methods, and apparatus for multiplexing addresses and data at a memory interface such that multiple data widths are provided without the need to change a motherboard or other printed...
7584336 Systems and methods for providing data modification operations in memory subsystems  
Systems and methods for providing data modification operations in memory subsystems. Systems include a plurality of memory devices, a memory controller, one or more memory busses connected to the...
7581073 Systems and methods for providing distributed autonomous power management in a memory system  
Systems and methods for providing distributed autonomous power management in a memory system. Embodiments include a memory system for storing and retrieving data for a processing system. The...
7580997 State recovery  
A method of recovering the state of a system, which system comprises at least one counter, which counter represents an instantaneous state of an entity in a system. The counter will increase in...