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7870326 Multiprocessor system and method thereof  
A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the...
7865674 System for enhancing the memory bandwidth available through a memory module  
A memory system is provided that enhances the memory bandwidth available through a memory module. The memory system includes a memory hub device integrated in a memory module. The memory system...
7865761 Accessing multiple non-volatile semiconductor memory modules in an uneven manner  
A data storage apparatus (e.g., a flash memory appliance) includes a set of memory modules, an interface and a main controller coupled to the each memory module and to the interface. Each memory...
7865656 Storage controller and storage control method  
A storage controller that can control memory addresses even when a memory module having a different device configuration than an already mounted memory module is added as an expansion module. More...
7865672 Electronic system with first and second electronic units electrically communicable with each other  
An electronic system has a first electronic unit for carrying out a first predetermined operation and a second electronic unit for carrying out a second predetermined operation. The first and...
7861052 Computer system having an expansion device for virtualizing a migration source logical unit  
A migration destination storage creates an expansion device for virtualizing a migration source logical unit. A host computer accesses an external volume by way of an access path of a migration...
7861030 Method and apparatus for updating data in ROM using a CAM  
A method for providing field updates through the use of a memory emulation circuit with a content addressable memory (CAM) as the intelligent portion of the emulation circuit's arbiter. CAM...
7861014 System for supporting partial cache line read operations to a memory module to reduce read data traffic on a memory channel  
A memory system is provided that supports partial cache line read operations to a memory module to reduce read data traffic on a memory channel. The memory system comprises a memory hub device...
7861039 Distributed FIFO  
Circuits, methods, and apparatus for FIFO memories made up of multiple local memory arrays. These embodiments limit the number and length of interconnect lines that are necessary to join two or...
7856541 Latency aligned volume provisioning methods for interconnected multiple storage controller configuration  
A system is composed of multiple storage control modules, which are connected to each other via interconnects. The aforesaid interconnects connecting the storage control modules may cause certain...
7856528 Method and apparatus for protecting data using variable size page stripes in a FLASH-based storage system  
Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of using variable size page stripes in the memory system. The controller is...
7849255 Pseudo-bidimensional randomly accessible memory using monodimensional sequentially-accessiblle memory structure  
A memory comprises at least one array of memory elements, a partition of the at least one array into a plurality of sub-arrays of the memory elements, and an array configuration circuit for...
7848855 Method for operating a system of modular structure, in particular a process automation system  
There is described a method for operating a system of modular structure, which can be extended during operation by adding modules that consume electrical energy, in particular a process automation...
7844771 System, method and storage medium for a memory subsystem command interface  
A system for implementing a memory subsystem command interface, the system including a cascaded interconnect system including one or more memory modules, a memory controller and a memory bus. The...
7844773 Refresh circuit and refresh method in semiconductor memory device  
A refresh method for a semiconductor memory device having more than one bank group is provided. The refresh method may include applying an all-refresh command to one the bank groups, determining...
7840744 Rank select operation between an XIO interface and a double data rate interface  
In an aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) generating a first command and associated address of a first type that...
7840762 Multi-path accessible semiconductor memory device having mailbox areas and mailbox access control method thereof  
A multipath accessible semiconductor memory device having a mailbox area and a mailbox access control method thereof are provided. The semiconductor memory device includes N number of ports, at...
7836263 Nonvolatile memory controlling method and nonvolatile memory controlling apparatus  
A nonvolatile-memory controlling method is disclosed which continuously accesses a plurality of memory banks structured so as to have each memory bank accessible independently. The method...
7822911 Memory device and method with on-board cache system for facilitating interface with multiple processors, and computer system using same  
A memory device includes an on-board cache system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The cache...
7822910 Method of flexible memory segment assignment using a single chip select  
Embodiments of the invention may generally provide techniques that allow mapping of memory devices in a multi-chip package (MCP) to memory segments of an address space. For some embodiments, a...
7818488 Memory module with registers  
Pairs of registers with reduced pins are disposed to overlap on front and back surfaces of a memory module. An input signal INS is transferred through the registers in series in a daisy chain...
7818501 Rebalancing of striped disk data  
Provided are a method, system, and article of manufacture, where a plurality of extents are stored in a first set of storage units coupled to a controller. A determination is made that a second...
7814239 Memory devices implementing clock mirroring scheme and related memory systems and clock mirroring methods  
A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first...
7805561 Method and system for local memory addressing in single instruction, multiple data computer system  
A single instruction, multiple data (“SIMD”) computer system includes a central control unit coupled to 256 processing elements (“PEs”) and to 32 static random access memory (“SRAM”) devices. Each...
7797477 File access method in a storage system, and programs for performing the file access  
In order to manage the various types of attribute information within the storage system, the storage system includes the following databases within a file-access controlling memory: a database for...
7793043 Buffered memory architecture  
A memory architecture includes at least one unbuffered dual inline memory module (DIMM). At least one advanced memory buffer (AMB) provides an interface between the at least one DIMM and a host...
7793034 Memory controller and method for multi-path address translation in non-uniform memory configurations  
In a method of translating a physical memory address to a device address in a device memory space, a fast address translate of the physical memory address, adapted to translate addresses in...
7788633 Bank note processing machine and method for operating bank note processing machine  
A bank note processing machine includes a plurality of sensors, a transport system, an input/output device, a control device and an interface. The control device has a memory configured to control...
7788471 Data processor and methods thereof  
A system and method for performing vector arithmetic is disclosed. The method includes loading two operand vectors, each composed of a number of vector elements, into two storage locations. A...
7787311 Memory with programmable address strides for accessing and precharging during the same access cycle  
Embodiments of the present disclosure provide methods, apparatuses and systems including a storage configured to store and output multiple address strides of varying sizes to enable access and...
7788487 Data processing apparatus  
In a data processing apparatus that switches between a secure mode and a normal mode during execution, the secure mode allowing access to secure resources to be protected, the normal mode not...
7783827 Data processor having a memory controller with cache memory  
The data processor enhances the bus throughput or data throughput of an external memory, when there are frequent continuous reads with a smaller data size than the data bus width of the external...
7783627 Database retrieval with a unique key search on a parallel computer system  
An apparatus and method retrieves a database record from an in-memory database of a parallel computer system using a unique key. The parallel computer system performs a simultaneous search on each...
RE41589 Memory system performing fast access to a memory location by omitting the transfer of a redundant address  
A data processing system including a processor LSI and a DRAM divided into banks, for increasing a ratio of using a fast operation mode for omitting transfer of a row address to the DRAM and for...
7784057 Single-stack model for high performance parallelism  
A method and apparatus are provided for operating a processor. The method comprising the steps of providing a single call stack for execution of a plurality of tasks that operate on the processor,...
7779198 Method and apparatus of multiple abbreviations of interleaved addressing of paged memories  
An interleaved addressing technique for addressing a plurality of memory banks (12, 72) uses a plurality of abbreviated interleaves (0, 1, . . . 2B−1) each addressing more than one and less than...
7774535 Memory system and memory device  
According to one embodiment, a first memory device is configured to receive write data from a controller and transmit read data to the controller via a first data pin included in the first memory...
7752398 Multi-port memory architecture for storing multi-dimensional arrays I  
An N-port memory architecture is disclosed that stores multi-dimensional arrays so that: (1) N contiguous elements in a row can be accessed without blocking, (2) N contiguous elements in a column...
7752249 Memory-based fast fourier transform device  
A memory-based Fast Fourier Transform device is provided, which adopts single-port random access memory (RAM), rather than dual-port RAM, as a storage, and the circuit area of the FFT device is...
7752364 Apparatus and method for communicating with semiconductor devices of a serial interconnection  
A system controller communicates with devices in a serial interconnection. The system controller sends a read command, a device address identifying a target device in the serial interconnection...
7752379 Managing write-to-read turnarounds in an early read after write memory system  
Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read...
7739423 Bulk transfer of information on network device  
A network device for processing packets. The network device includes a CPU processing module for transmitting information between at least one memory location on the network device and an external...
7739448 System and method for managing storage networks and providing virtualization of resources in such a network  
This invention is a system and method for managing one or more data storage networks using a new architecture. A method for handling logical to physical mapping is included in one embodiment with...
7734865 Storage system using flash memory modules logically grouped for wear-leveling and raid  
A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory...
7730268 Multiprocessor system having an input/output (I/O) bridge circuit for transferring data between volatile and non-volatile memory  
A disclosed circuit includes circuitry for coupling to a volatile memory, circuitry for coupling to a nonvolatile NAND flash memory, and circuitry that: (i) receives a volatile memory request from...
7730254 Memory buffer for an FB-DIMM  
A memory buffer for an FB-DIMM having a first input/output interface for communicating with a memory controller at a first payload data rate and a second input/output interface for communicating...
7725641 Memory array structure and single instruction multiple data processor including the same and methods thereof  
A memory may be configured to rearrange and store data to enable a conflict free mode for a memory access pattern required by a coder-decoder(codec) and configured to output a plurality of data...
7721130 Apparatus and method for switching an apparatus to a power saving mode  
An apparatus being connectable as a latch stage into a asynchronous latch chain comprises a reception interface, wherein upon receipt of the first signal at the reception interface, the apparatus...
7721066 Efficient encoding for detecting load dependency on store with misalignment  
In one embodiment, an apparatus comprises a queue comprising a plurality of entries and a control unit coupled to the queue. The control unit is configured to allocate a first queue entry to a...
7721011 Method and apparatus for reordering memory accesses to reduce power consumption in computer systems  
A reordering command queue for reordering memory accesses in a computer system. The reordering command queue may reduce the power that is typically used up in computer systems when performing...