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8032688 Micro-tile memory interfaces  
In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage...
8032804 Systems and methods for monitoring a memory system  
Systems and methods are disclosed herein, including those that operate to monitor a first set of operational parameters associated with a memory vault, to adjust a second set of operational...
8028257 Structure for data bus bandwidth scheduling in an FBDIMM memory system operating in variable latency mode  
A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for scheduling the servicing of data requests, using the variable latency...
8019948 Multi-path accessible semiconductor memory device having mailbox areas and mailbox access control method thereof  
A multipath accessible semiconductor memory device having a mailbox area and a mailbox access control method thereof are provided. The semiconductor memory device includes N number of ports, at...
8020056 Memory channel with bit lane fail-over  
Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory...
8019919 Method for enhancing the memory bandwidth available through a memory module  
A method for enhancing the memory bandwidth available through a memory module of a memory system is provided. The memory system includes a memory hub device integrated in a memory module. The...
8019927 Electronic tag system having bank status and controlling method thereof  
An electronic tag system, an electronic tag, and a controlling method thereof according to the present invention include an electronic tag that includes a memory having a divided band and a bank...
8010775 Method and related apparatus for reducing CHIPSET power consumption  
A method for reducing computer system power consumption. The computer system includes a memory module having a plurality of address pins, and a chipset having a plurality of driving units for...
8010580 Information browser, method of controlling same, and program  
A meta-information-read unit, a display-cache unit, a pre-reading-cache unit, a display-state-management unit, an operation-input unit, a meta-information-pre-reading unit, and an...
8006063 Management method and a management system for volume  
It is made possible to update information registered in a database of iSNS, SLP and the like in response to a configurational change in a storage device, and for a host computer to discover a disk...
8006028 Enabling memory module slots in a computing system after a repair action  
Methods, systems, and products are disclosed for enabling memory module slots in a computing system after a repair action, the computing system having a plurality of memory module slots and having...
8006057 Memory devices with buffered command address bus  
Circuits and methods are provided that alleviate overloading of the command address bus and limit decreases in command address bus bandwidth to allow increased numbers of memory modules to be...
8001319 Semiconductor storage device  
A semiconductor storage apparatus is coupled with a system bus to receive a write request accompanied with first and second blocks of data, which are stored in nonvolatile semiconductor memories....
7996646 Efficient encoding for detecting load dependency on store with misalignment  
In one embodiment, an apparatus comprises a queue comprising a plurality of entries and a control unit coupled to the queue. The control unit is configured to allocate a first queue entry to a...
7996602 Parallel memory device rank selection  
A translator of an apparatus in an example selects one or more ranks of parallel memory devices from a plurality of available ranks of parallel memory devices in a plurality of double data rate...
7996647 Enhanced microprocessor or microcontroller  
A processor device has a data memory with a linear address space, the data memory being accessible through a plurality of memory banks. At least a subset of the memory banks are organized such...
7996632 Device for misaligned atomics for a highly-threaded x86 processor  
A multithreaded processor with a banked cache is provided. The instruction set includes at least one atomic operation which is executed in the L2 cache if the atomic memory address source data is...
7996641 Structure for hub for supporting high capacity memory subsystem  
A design structure is provided for a hub for use in a high-capacity memory subsystem in which memory modules arranged in one or more clusters, each attached to a respective hub which in turn is...
7996613 Electronic device using memory to expand storage capacity  
The present invention discloses an electronic device using a memory to expand storage capacity, and the device includes a main board and a data storage module. The main board includes at least one...
7996597 Mapping address bits to improve spread of banks  
A device may include a group of requestors issuing requests, a memory that includes a set of memory banks, and a control block. The control block may receive a request from one of the requestors,...
7984217 Data transmission method, serial bus system, and switch-on unit for a passive station  
In a serial bus system data in the form of telegrams, representing process images of control tasks of the active station, are transmitted to the connected passive stations, and the process data...
7984222 Systems for providing performance monitoring in a memory system  
Systems for providing performance monitoring in a memory system. The memory system includes a memory controller, a plurality of memory devices, a memory bus and a memory hub device. The memory...
7978516 Flash memory controller having reduced pinout  
Disclosed is a flash memory controller connected to a flash memory module. The pin-out of the flash memory controller combines ready-busy and chip-select signals. In one embodiment, the flash...
7979632 Storage system including a fast storage device for storing redundant data  
A computer storage system includes a controller, a first storage device and a second storage device including at least one fast storage device. The controller is configured to perform data...
7979622 Memory access method  
A memory access method intended for a memory required to provide an interval of a predetermined number of clock cycles or longer between successive occurrences of access when the same bank is...
7970980 Method and apparatus for accessing memory in a computer system architecture supporting heterogeneous configurations of memory structures  
A computer system includes at least one processor, multiple memory modules embodying a main memory, a communications medium for communicating data between the at least one processor and main...
7970985 Adaptive deterministic grouping of blocks into multi-block units  
The present invention presents techniques for the linking of physical blocks of a non-volatile memory into composite logical structures or “metablocks”. After determining an initial linking of...
7970986 Storage system using flash memories and wear-leveling method for the same system  
A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory...
7966444 Reconfigurable memory module and method  
A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory...
7966443 Memory systems including memory devices coupled together in a daisy-chained arrangement  
A memory system having a plurality of memory devices and a memory controller. The memory devices are coupled to one another in a chain. The memory controller is coupled to the chain and configured...
7966446 Memory system and method having point-to-point link  
A memory system includes a controller for generating a control signal and a primary memory for receiving the control signal from the controller. A secondary memory is coupled to the primary...
7958305 System and method for managing storage networks and providing virtualization of resources in such a network  
This invention is a system and method for managing one or more data storage networks using a new architecture. A method for handling logical to physical mapping is included in one embodiment with...
7958263 Address reduction for data storage enclosures  
A data storage enclosure management system of a plurality of service processors is configured to communicate externally via a pair of FC-AL loops. Lead and subsidiary service processors are...
7953921 Directed auto-refresh synchronization  
In a directed auto-refresh (DARF) mode, refresh commands are issued by a controller, and refresh row and bank addresses are maintained internally to a memory module. A bank address counter...
7934047 Memory module and memory system  
A memory module includes a plurality of ranks that each include a first pin group and a second pin group for receiving external pin signals, and a rank selecting unit included in each of the...
7930465 Determining operation mode for semiconductor memory device  
A semiconductor memory device capable of determining an operation mode by using states of data pins, and an operation mode determining method for the same are disclosed. The semiconductor memory...
7930492 Memory system having low power consumption  
A memory system selectively sets signaling modes based on stack position information. The memory system includes a memory module having at least one semiconductor memory device and a memory...
7925912 Method and apparatus for fine edge control on integrated circuit outputs  
A device for adjusting the timing of at least one edge of an output pulse created in response to a reference pulse is disclosed. Such a device may include a first memory circuit having two or more...
7913030 Storage device with transaction logging capability  
In one aspect, a system for indexing transactions over a shared bus is described. In various embodiments, the system includes a host controller and a plurality of storage devices in communication...
7908530 Memory module and on-line build-in self-test method thereof for enhancing memory system reliability  
A memory module including a plurality of memory banks, a memory control unit, and a built-in self-test (BIST) control unit is provided. The memory banks store data. The memory control unit...
7907470 Multi-column addressing mode memory system including an integrated circuit memory device  
A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit...
7900010 System and method for memory allocation management  
A memory manager for a system, a system that includes the memory manager and a method of using thereof are provided. The memory manager manages memory allocations in at least a memory. The memory...
7899984 Memory module system and method for operating a memory module  
A memory module system, a memory module, a buffer device, a memory module printed circuit board, and to a method for operating a memory module is disclosed. In one embodiment, the memory module...
7900018 Embedded system and page relocation method therefor  
Provided are an embedded system and a method for relocating memory pages therefor. The embedded system includes a processor, a data relocating circuit for receiving a logical address from the...
7895484 Semiconductor device, memory system and control method of the semiconductor device  
A semiconductor device including a logic circuit and a test circuit is provided which comprises: a logic signal terminal that supplies a signal to the logic circuit; a latch circuit that latches a...
7890687 Motherboard and interface control method of memory slot thereof  
The invention provides a motherboard and an interface control method of a memory slot thereof. The motherboard includes a plurality of slot groups, a bus, and an interface controller. Each of the...
7882324 Method and apparatus for synchronizing memory enabled systems with master-slave architecture  
Embodiments of the invention generally provide a system, method and memory device for accessing memory. One embodiment includes synchronization circuitry configured to determine timing skew...
7873776 Multiple-core processor with support for multiple virtual processors  
A multiple-core processor with support for multiple virtual processors. In one embodiment, a processor may include a cache including a number of cache banks, a number of processor cores and...
7873800 Address generator for an interleaver memory and a deinterleaver memory  
Method and device for generating an address value for addressing an interleaver memory. Consecutive address fragments to which a most significant bit(s) is to be appended are generated. Only a...
7870351 System, apparatus, and method for modifying the order of memory accesses  
Systems and methods for controlling memory access operation are disclosed. The system may include one or more requestors performing requests to memory devices. Within a memory controller, a...