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8190809 Shunted interleave for accessing plural memory banks, particularly those having partially accessed cells containing data for cache lines  
A bank select device has a plurality of addressable locations and a plurality of storage locations correlated to each other so that each storage location is correlated to plural addressable...
8185711 Memory module, a memory system including a memory controller and a memory module and methods thereof  
A memory module, a memory system including a memory controller and a memory module and methods thereof. The example memory module may include a plurality of memory units each having an interface...
8180939 Memory devices implementing clock mirroring scheme and related memory systems and clock mirroring methods  
A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first...
8180974 System, apparatus, and method for modifying the order of memory accesses  
Systems and methods for controlling memory access operations are disclosed. The system may include one or more requestors performing requests to memory devices. Within a memory controller, a...
8166316 Single interface access to multiple bandwidth and power memory zones  
In an embodiment, a system comprises a first memory module interface unit (MMIU) configured to couple to a first one or more memory modules, and a second MMIU configured to couple to a second one...
8166230 Memory systems and methods of initializing the same  
A memory system is provided includes a host processor, and a plurality of cascade connected memory cards connected to the host processor. Each of the memory cards stores a same default relative...
8166228 Non-volatile memory system and method for reading and storing sub-data during partially overlapping periods  
A non-volatile memory system and a method for reading data therefrom are provided. The data comprises a first sub-data and a second sub-data. The non-volatile memory system comprises a first...
8154947 Multi-column addressing mode memory system including an integrated circuit memory device  
A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit...
8151030 Method of increasing DDR memory bandwidth in DDR SDRAM modules  
The present invention provides a method of increasing DDR memory bandwidth in DDR SDRAM modules. DDR memory has an inherent feature called the Variable Early Read command, where the read command...
8151031 Local memories with permutation functionality for digital signal processors  
A digital signal processor (DSP) co-processor according to a clustered architecture with local memories. Each cluster in the architecture includes multiple sub-clusters, each sub-cluster capable...
8151010 Memory devices implementing clock mirroring scheme and related memory systems and clock mirroring methods  
A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first...
8145877 Address generation for quadratic permutation polynomial interleaving  
For address generation, a block size and a skip value are obtained, and at least one address, at least one increment value, and a step value are initialized. For a count index not in excess of a...
8140739 Flash memory based storage devices utilizing magnetoresistive random access memory (MRAM) to store files having logical block addresses stored in a write frequency file buffer table  
A flash memory based storage device may utilize magnetoresistive random access memory (MRAM) as at least one of a device memory, a buffer, or high write volume storage. In some embodiments, a...
8140783 Memory system for selectively transmitting command and address signals  
A system includes a memory controller adapted to output address signals, command signals and select signals; a plurality of memory modules; and a plurality of buses each corresponding to one of...
8135897 Memory architecture  
A memory architecture is presented. The memory architecture comprises a first memory and a second memory. The first memory has at least a bank with a first width addressable by a single address....
8134884 Semiconductor memory device  
A semiconductor memory device comprises a memory unit having a first and a second port and including plural banks; a bank address conversion circuit operative to convert a first bank address fed...
8136116 Device allocation utilizing job information, storage system with a spin control function, and computer thereof  
This invention provides a storage system coupled to a computer that executes data processing jobs by running a program, comprising: an interface; a storage controller; and disk drives. The storage...
8134875 Data storage system with removable memory module having parallel channels of DRAM memory and flash memory  
A data storage system includes a first circuit board, a plurality of sockets coupled to the first circuit board, an connector coupled to each of the sockets for coupling each of the sockets to...
8135999 Disabling outbound drivers for a last memory buffer on a memory channel  
Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory...
8135935 ECC implementation in non-ECC components  
A method and apparatus for implementation of error correction code (ECC) checking in non-ECC-compliant components. The method includes receiving a logical address, wherein the logical address maps...
8131913 Selective broadcasting of data in series connected devices  
A method and system for the selective broadcasting of commands to a subset of a plurality of devices connected in series to a memory controller, where each of the plurality of devices has a unique...
8127069 Memory device including self-ID information  
Disclosed is a memory device including self-ID information. The memory device has a storage unit for storing information related to the memory device, such as a manufacturing factory, a...
8116306 Shared memory system  
A shared memory system including: a shared memory includes a plurality of memory banks; a plurality of input ports; a plurality of input buffers; and a controller for controlling writing-into and...
8112580 Disk drive having multiple disk surfaces accessible by a read/write head and nonvolatile memory for continuous data transfer  
A magnetic recording hard disk drive (HDD) has at least one read/write head that accesses more than one disk surface. The HDD is able to transfer data to and from the host computer seamlessly...
8112608 Variable-width memory  
Described is a memory system in which the memory core organization changes with device width. The number of physical memory banks accessed reduces with device width, resulting in reduced power...
8108647 Digital data architecture employing redundant links in a daisy chain of component modules  
A communications architecture utilizes modules arranged in a daisy-chain, each module supporting multiple input and output ports. Point-to-point links are arranged so that a first output link of...
8108648 Various methods and apparatus for address tiling  
Various methods and apparatus are described for a memory scheduler. The memory scheduler couples to a target memory core that includes a bank of memories. The memory scheduler contains two or more...
8108629 Method and computer for reducing power consumption of a memory  
Provided is a method of managing, in a computer including a processor and a memory that stores information referred to by the processor, the memory. The memory includes a plurality of memory...
8102690 Bank re-assignment in chip to reduce IR drop  
A chip system that has reduced power consumption under specific operational modes includes: a DDR3 chip that includes: a plurality of pads, disposed at the center of the DDR3 chip; and an array of...
8103818 Memory module and auxiliary module for memory  
In a memory module 100, an address generating circuit 120, using the highest order bit of a row address output by a memory controller 12, will generate a highest order bit BA2 of a bank address...
8099567 Reactive placement controller for interfacing with banked memory storage  
An invention is provided for a reactive placement controller for interfacing with a banked memory storage. The reactive placement controller includes a read/write module, which is coupled to a...
8095747 Memory system and method  
In an embodiment, an apparatus includes a memory controller configured to control first and second memory components. A point-to-point data bus configured to pass data between the memory...
8094654 Information transfer in electronic modules  
An electronic assembly includes electronic modules connected in a series circuit such that a particular number of input connections of one of the electronic modules is connected with the...
8090896 Address generation for multiple access of memory  
A memory bank has a plurality of memories. In an embodiment, a forward unit applies logical memory addresses to the memory bank in a forward twofold access order, a backward unit applies logical...
8086783 High availability memory system  
A memory system with high availability is provided. The memory system includes multiple memory channels. Each memory channel includes at least one memory module with memory devices organized as...
8078791 Ordering refresh requests to memory  
A device may generate a refresh signal that identifies a beginning of a refresh interval, determine the availability of banks of a memory device, and send refresh requests to the banks during the...
8078790 Fast unaligned cache access system and method  
A cache unit multiple memory towers, which can be independently addressed. Cache lines are divided among multiple towers. Furthermore, physical lines of the memory towers are shared by multiple...
8074010 Intelligent memory banks for storing vectors  
An intelligent memory bank for use with interleaved memories storing plural vectors comprises setup apparatus (96) receives an initial address (B+C+V+NMSK) and spacing data (D) for each vector....
8069299 Banded indirection for nonvolatile memory devices  
Methods, apparatuses, and computer program products that enable banded indirection for nonvolatile memory devices, such as flash memory devices, are disclosed. One or more embodiments comprise a...
8065475 Registered dual in-line memory module having an extended register feature set  
A registered dual in-line memory module is configured with multiple random access memory chips and a DRAM register configured to receive address and control signals from a memory controller. The...
8060708 Multiprocessor system having an input/output (I/O) bridge circuit for transferring data between volatile and non-volatile memory  
A disclosed circuit includes circuitry for coupling to a volatile memory, circuitry for coupling to a nonvolatile NAND flash memory, and circuitry that: (i) receives a volatile memory request from...
8060692 Memory controller using time-staggered lockstep sub-channels with buffered memory  
Memory control techniques for dual channel lockstep configurations are disclosed. In accordance with one example embodiment, a memory controller issues two burst-length 4 DRAM commands to two...
8055852 Memory device and method having on-board processing logic for facilitating interface with multiple processors, and computer system using same  
A memory device includes an on-board processing system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The...
8050134 Multi-column addressing mode memory system including an integrated circuit memory device  
A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit...
8051239 Multiple access for parallel turbo decoder  
A memory bank contains a plurality of memories, a first Butterfly network is configured to apply memory addresses to the memory bank, and a second Butterfly network is configured to pass data to...
8041903 Processor and method for controlling memory  
A processor and a memory controlling method. The processor enables a Scratch-Pad Memory (SPM) to prepare data that a processor core intends to process, using a data management unit including a...
8041907 Method and system for efficient space management for single-instance-storage volumes  
A method and system for efficient space management for single-instance-storage volumes is provided. A backup module storing data within a collection of containers according to access locality and...
8036061 Integrated circuit with multiported memory supercell and data path switching circuitry  
An integrated circuit. The integrated circuit includes a plurality of memory requesters and a memory supercell. The memory supercell includes a plurality of memory banks each of which forms a...
8036012 Device for controlling the activity of modules of an array of memory modules  
A memory device includes an array of memory modules, a global controller, and a local controller for each memory module in the array of memory modules being configured to deliver to the global...
8037247 Methods, computer program products, and systems for providing an upgradeable hard disk  
Methods, computer program products and systems for providing an upgradeable hard disk. The system includes a plurality of memory card slots and a controller. The controller includes a host...