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7107386 Memory bus arbitration using memory bank readiness  
A method, apparatus, and computer program product includes identifying a plurality of memory transactions to be sent over a memory bus to a memory having a plurality of memory banks, each memory...
7107412 Distributed processor memory module and method  
A memory module for a computer system is removably coupled to a computer system mother-board having a data bus and an address bus. The memory module includes a memory interface, a program memory...
7103708 PERFORMING LOOKUP OPERATIONS USING ASSOCIATIVE MEMORIES OPTIONALLY INCLUDING MODIFYING A SEARCH KEY IN GENERATING A LOOKUP WORD AND POSSIBLY FORCING A NO-HIT INDICATION IN RESPONSE TO MATCHING A PARTICULAR ENTRY  
Methods and apparatus are disclosed for performing lookup operations using associative memories, including, but not limited to modifying search keys within an associative memory based on...
7099989 System and technique to reduce cycle time by performing column redundancy checks during a delay to accommodate variations in timing of a data strobe signal  
A memory device includes a memory cell array, an addressing circuit, a data communication circuit and a control circuit. The addressing circuit receives first signals that are indicative of an...
7099988 Apparatus and method to read information from an information storage medium  
A method to read (N) sequential files written to an information storage medium, and then skip the next (M) sequential files. The method initially identifies the (M) files to be skipped. After...
7096324 Embedded processor with dual-port SRAM for programmable logic  
Methods and apparatus for programmable logic devices including embedded processors having a dual-port SRAMs. A programmable logic integrated circuit includes a programmable logic portion having a...
7093059 Read-write switching method for a memory controller  
A system includes a memory device. The memory device has a first bank and a second bank. A memory controller has a write request queue to store write requests. When a read bank conflict exists...
7093062 Flash memory data bus for synchronous burst read page  
Memory device is described that utilizes a reduced number of sense amplifiers to sense the data bits of a selected column page. The sense amplifiers are multiplexed and the read data values...
7089558 Inter-partition message passing method, system and program product for throughput measurement in a partitioned processing environment  
A partitioned processing system is disclosed wherein a workload calculation is implemented for at least one partition. CPU utilization and I/O throughput information is used in calculating resource...
7089379 Large high bandwidth memory system  
A memory system is divided into memory subsystems. Each subsystem includes a slave controller. Each slave controller is coupled to a serial link. A master controller is coupled to the slave...
7080225 Method and apparatus for managing migration of data in a computer system  
Methods and apparatus for migrating a data set. In one embodiment, a migration is paused. In another embodiment, for a migration of data between multiple source/target groups, the migration is...
7080193 Flash memory with accessible page during write  
A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication...
7076617 Adaptive page management  
Machine-readable media, methods, and apparatus are described which process memory transactions. In some embodiments, a memory controller of a processor and/or chipset may adaptively determine...
7076618 Memory controllers with interleaved mirrored memory modes  
In some embodiments, a memory controller includes first and second memory channel interfaces and memory access control circuitry. The memory access control circuitry is to send first and second...
7073012 System and method for interleaving data in a communications device  
A system and method is provided for interleaving data in a communications device. The system includes a memory for storing symbols of a data block, a read module and a write module, each of which...
7072986 System and method for displaying storage system topology  
A management display method according to each type of interfaces and devices is provided in an environment where host computers are interconnected with storage apparatuses through plural types of...
7073014 Synchronous non-volatile memory system  
A computer system comprises a memory controller and a synchronous non-volatile memory device coupled to the memory controller via a main memory bus. The synchronous non-volatile memory device has...
7065608 Apparatus for recording data and method for writing data to flash memory  
The present invention provides an apparatus for recording data, including a storage unit ( 4 ) for reading out management information stored in the flash memory ( 2 ) to store read out management...
7062597 Integrated circuit buffer device  
A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device...
7062630 Storing device for writing data onto a plurality of installed storing mediums, storing control method for the storing device, and program thereof  
A storing device can reduce the frequency of the saving operation at a step of rewriting data on the storing mediums. Where q is a size of all the data to write in storing mediums, m is the number...
7058756 Circuit for implementing special mode in packet-based semiconductor memory device  
Disclosed is a circuit for implementing a special mode in a packet-based semiconductor memory device, which performs the special mode in the same manner as a normal operation without changing the...
7055012 Latency reduction using negative clock edge and read flags  
A method of selecting CAS latencies in a system. Specifically, a system which includes a plurality of memory devices and a memory controller is provided. Because different memory devices may have...
7051171 Method and system for providing a multi-channel interleaver/deinterleaver using SDRAM  
A deinterleaver for performing high-speed multi-channel forward error correction using external SDRAM is provided. According to one exemplary aspect, the deinterleaver performs both read and write...
7051178 Burst write in a non-volatile memory device  
A synchronous flash memory has been described that includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The synchronous...
7047371 Integrated memory having a memory cell array containing a plurality of memory banks, and circuit configuration having an integrated memory  
An integrated memory has at least two connection panels, which can be operated independently of one another, for external communication by the memory. In addition, a control circuit produces a...
7047385 High-speed memory for use in networking systems  
A memory integrated circuit includes an array of high-speed memory blocks coupled to the address input interface and data output interface of the integrated circuit by address and data pipelines...
7043598 Method and apparatus for dynamic memory refreshing  
In a memory device with a bank of N memory blocks, an address is generated for a first and a second one of the blocks. The first and second addresses include addresses for current first and second...
7043617 System supporting multiple memory modes including a burst extended data out mode  
A system is capable of receiving Fast Page mode, Extended Data Out mode, Burst Extended Data Out mode, or a combination of these memory devices. A method of determining the type of memory present...
7038964 Access to a common memory in which a priority access to a non-active bank is prepared during a non-priority access to a different bank  
Access of multiple data processing circuits to a common memory having several banks is managed, the memory being connected to one or several circuits for processing ordinary data and to a circuit...
7035161 Semiconductor integrated circuit  
An I/O interface circuit immediately close to a bank having a plurality of memory cells and an I/O circuit is directly connected to data line pairs via a switching circuit. Another I/O interface...
7035962 Pipelined packet-oriented memory system having a unidirectional command and address bus and a bidirectional data bus  
A memory system having at least one memory subsystem and using a packet protocol communicated over a command and address bus and at least one data bus. The memory subsystems are pipelined to...
7028209 I2C repeater with voltage translation  
A bus repeater with voltage conversion and multiplexing circuits for use between devices with incompatible voltage levels communicating over inter-integrated circuit (I2C) buses. Bi-directional...
7028156 Use of read data tracking and caching to recover from data corruption  
In a system in which read data tracking and caching is used to recover from data corruption, a first request to read data from a primary data mirror is received from a computer system. Data is read...
7028135 Multiple partition memory command user interface  
A multiple partition memory array has a command user interface for each partition, and a logic interface. The logic interface receives signals from each of the command user interfaces to restrict...
7024515 Methods and apparatus for performing continue actions using an associative memory which might be particularly useful for implementing access control list and quality of service features  
Methods and apparatus are disclosed for use with an associative memory, such as for, but not limited to implementing access control list and quality of service features in a communications or...
7024578 Array of synchronized memory modules  
A memory apparatus includes a memory module array having several memory modules. Each memory module has a synchronization connection for receiving a synchronization signal for synchronizing the...
7020757 Providing an arrangement of memory devices to enable high-speed data access  
A memory subsystem includes multiple memory modules coupled by point-to-point links. A memory controller is coupled by a point-to-point link to a first memory module, which is turn is coupled by...
7020758 Context sensitive storage management  
The invention relates to methods and associated systems for managing application workloads and data storage resources. Data storage resources my be mapped to logical addresses associated with...
7020736 Method and apparatus for sharing memory space across mutliple processing units  
A method and apparatus for sharing memory space of multiple memory units by multiple processing units are described. In an embodiment, a method includes storing a set of data across more than one...
7017017 Memory controllers with interleaved mirrored memory modes  
In some embodiments, a memory controller includes first and second memory channel interfaces and memory access control circuitry. The memory access control circuitry is to send first and second...
7017002 System featuring a master device, a buffer device and a plurality of integrated circuit memory devices  
A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device...
7010654 Methods and systems for re-ordering commands to access memory  
Methods and systems for re-ordering commands to access memory are disclosed. Embodiments may receive a first command to access a memory bank of the memory and determine a penalty associated with...
7010656 Method and apparatus for memory management  
In some embodiments, an electronic device includes a processor, a physical memory coupled to the processor, and a storage medium coupled to the processor. The storage medium may store instructions...
7010642 System featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices  
A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device...
7007130 Memory system including a memory module having a memory module controller interfacing between a system memory controller and memory devices of the memory module  
A system that has a system memory controller and a memory module. The memory module includes a memory module controller coupled to the system memory controller and a plurality of memory devices...
7003640 Power-aware adaptation in an information server  
An information server with power-aware adaptation that enables power reduction while minimizing the performance impact of power reduction. An information server according to the present techniques...
7003618 System featuring memory modules that include an integrated circuit buffer devices  
A computer system includes a controller device having an interface disposed on a circuit board. A first socket is disposed on the circuit board and receives a first memory module having a first...
7003630 Mechanism for proxy management of multiprocessor storage hierarchies  
A method and apparatus within a processing environment is provided for proxy management of a plurality of proxy caches connected to a plurality of processing elements or cores within a unified...
7003622 Semiconductor memory  
A semiconductor memory includes a redundant RAM disposed independently of at least one regular RAM, the redundant RAM having redundant memory elements by which defective memory elements of the...
7003639 Memory controller with power management logic  
A memory controller controls access to, and the power state of a plurality of dynamic memory devices. A cache in the memory controller stores entries that indicate a current power state for a...
Matches 251 - 300 out of 1063 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >