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8364882 System and method for executing full and partial writes to DRAM in a DIMM configuration  
In an embodiment of the invention, a host or other controller writing to multiple DRAMs in a DIMM configuration determines whether there is full write request to at least one of the multiple...
8359423 Using LPDDR1 bus as transport layer to communicate to flash  
One embodiment of the present invention relates to a method for communicating NOR-type flash specific memory commands from a DRAM memory controller to a NOR-type flash memory array without...
8352429 Systems and methods for managing portions of files in multi-tier storage systems  
The present disclosure presents a method for managing portions of files in multi-tier storage systems. The method may include identifying a file that is managed by an application and stored in a...
8347026 Memory device and memory device control method  
A memory device according to this invention includes: N internal memory read buses and N internal memory write buses each including a plurality of internal slots; N memory modules; an output data...
8347020 Memory access controller, systems, and methods for optimizing memory access times  
A configurable memory access controller and related systems and methods. In embodiments described herein, the configurable memory controller is adapted to provide a separate memory access...
8341328 Method and system for local memory addressing in single instruction, multiple data computer system  
A single instruction, multiple data (“SIMD”) computer system includes a central control unit coupled to 256 processing elements (“PEs”) and to 32 static random access memory (“SRAM”) devices. Each...
8332701 Address generation apparatus and method for quadratic permutation polynomial interleaver de-interleaver  
An address generation apparatus for a quadratic permutation polynomial (QPP) interleaver is provided. It comprises a basic recursive unit, and L recursive units represented by first recursive unit...
8332569 Nonvolatile memory system using data interleaving scheme  
A memory system comprises a plurality of nonvolatile memory devices configured for interleaved access. Programming times are measured and recorded for various memory cell regions of the...
8327057 Ordering write bursts to memory  
A device may receive requests intended for a memory that includes a number of banks, determine a number of the requests intended for each of the banks, determine an order for the requests based on...
8327058 Method and system for routing data in a parallel turbo decoder  
Described herein are system(s) and method(s) for routing data in a parallel Turbo decoder. Aspects of the present invention address the need for reducing the physical circuit area, power...
8321652 Process and method for logical-to-physical address mapping using a volatile memory device in solid state disks  
An embodiment of the invention relates to a mass storage device including a nonvolatile memory device with a plurality of memory management blocks and an address translation table formed with...
8296556 System and method for processing booting failure of system  
A method for processing booting failure of a computer system is adapted for being performed at a computer. The method includes the following steps. First, a parameter selecting signal is generated...
8296529 Write-once optical disc and method for recording management information thereon  
A write-once optical disc and a method and apparatus for recording management information on the disc are provided. The method includes recording an opened SRR information on a recording medium,...
8291167 System and method for writing cache data and system and method for reading cache data  
A system and a method for writing cache data and a system and a method for reading cache data are disclosed. The system for writing the cache data includes: an on-chip memory device, configured to...
8289760 Multi-mode memory device and method having stacked memory dice, a logic die and a command processing circuit and operating in direct and indirect modes  
Memory device systems, systems and methods are disclosed, such as those involving a plurality of stacked memory device dice and a logic die connected to each other through a plurality of...
8291157 Concurrent refresh in cache memory  
Concurrent refresh in a cache memory includes calculating a refresh time interval at a centralized refresh controller, the centralized refresh controller being common to all cache memory banks of...
8291174 Memory device and method having on-board address protection system for facilitating interface with multiple processors, and computer system using same  
A memory device includes an address protection system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The...
8285914 Banked memory arbiter for control memory  
A device includes a memory that includes a number of banks. The device receives requests for accessing the memory, determines the banks to which the requests are intended, determines one or more...
8281100 System and method for controlling timing of copy start  
A volume group is a group of two or more copy-source volumes and two or more copy-destination volumes. A computer system stores access rate information, which is information denoting an access...
8281062 Portable storage device supporting file segmentation and multiple transfer rates  
A storage device has two connectors for transferring data files: a first connector through which data files can be transferred at an accelerated speed, and a second connector through which data...
8275936 Load reduction system and method for DIMM-based memory systems  
A load reduction system and method for use with memory systems which include one or more DIMMs, each of which includes a circuit arranged to buffer data bytes being written to or read from the...
8266372 High bandwidth memory interface  
A DRAM system configured for high bandwidth communication, the system includes at least one DRAM having resistive termination devices within the DRAM, and a controller connected to the DRAM...
8259339 Image forming apparatus  
An image forming apparatus includes a memory that stores therein a control program, a central processing unit that executes the control program stored in the memory, a print engine controlled by...
8254992 Wireless docking system and pairing protocol for multiple dock environments  
A wireless docking system and method is provided for monitoring the use of one or more docking stations by multiple portable computers. The system and method provides for the intelligent...
8250295 Multi-rank memory module that emulates a memory module having a different number of ranks  
A transparent four rank memory module has a front side and a back side. The front side has a third memory rank stacked on a first memory rank. The back side has a fourth memory rank stacked on a...
8250330 Memory controller having tables mapping memory addresses to memory modules  
A memory controller includes ports and corresponding tables. Each port is receptive to one or more memory modules. Each table includes entries mapping memory addresses to the memory modules. Each...
8250297 High bandwidth memory interface  
This invention describes an improved high bandwidth chip-to-chip interface for memory devices, which is capable of operating at higher speeds, while maintaining error free data transmission,...
8244993 Memory chain  
A memory system having a plurality of memory devices and a memory controller. The memory devices are coupled to one another in a chain. The memory controller is coupled to the chain and configured...
8245003 Composite memory device, data processing method and data processing program  
A composite memory device, a data processing method and a data processing program can efficiently and selectively use a nonvolatile solid-state memory and a recording medium. The composite medium...
8239607 System and method for an asynchronous data buffer having buffer write and read pointers  
A system and method for facilitating the adjustment of timing parameters between a memory controller operating in a first clock domain and a memory device operating in a second clock domain. A...
8239650 Wirelessly configurable memory device addressing  
A memory device includes a plurality of memory modules and a memory management module. A memory module of the plurality of memory modules includes a plurality of memory cells and a memory...
8234461 Systems and method for data survivability  
Systems and a method for storing data are provided. The protected memory system includes a memory array including a plurality of memory modules each separately located with respect to each other...
8234528 Systems and methods for monitoring a memory system  
Systems and methods are disclosed herein, including those that operate to monitor a first set of operational parameters associated with a memory vault, to adjust a second set of operational...
8230196 Configurable partitions for non-volatile memory  
Example embodiments for configuring a non-volatile memory device may comprise configuring M physical partitions of the non-volatile memory into two or more banks, wherein the two or more banks...
8230147 Apparatus and method for communicating with semiconductor devices of a serial interconnection  
A system controller communicates with devices in a serial interconnection. The system controller sends a read command, a device address identifying a target device in the serial interconnection...
8230154 Fully associative banking for memory  
A system is provided that facilitates read access in a memory device. The system comprises a plurality of row addresses buffers that store high order addresses associated with one or more software...
8225026 Data packet access control apparatus and method thereof  
A data packet access control apparatus and a data packet access control method are disclosed. RAM resources in a data packet processing chip are used to implement a Bypass FIFO. The Bypass FIFO is...
8225027 Mapping address bits to improve spread of banks  
A device may include a group of requestors issuing requests, a memory that includes a set of memory banks, and a control block. The control block may receive a request from one of the requestors,...
8208796 Systems and methods for prioritizing the storage location of media data  
A digital media recorder includes a first storage device associated with the digital media recorder and an interface for removably attaching a second storage device to the digital media recorder....
8209478 Single-port SRAM and method of accessing the same  
A system and method for resolving request collision in a single-port static random access memory (SRAM) are disclosed. A first SRAM part and a second SRAM part of the single-port SRAM are accessed...
8209410 System and method for storage management  
A system and method for monitoring the storage estate of an organization using an interactive website that is configured to produce and display a novel set of key performance indicators (KPIs)...
8209458 System and method for DRAM bank assignment  
A network storage system includes an address adjusting module that includes a segmented packet receiver module that receives M sections of a segmented packet, where M is an integer greater than...
8209460 Dual memory chip package operable to access heterogeneous memory chips  
A dual-chip package is disclosed which includes at least two memory chips each of which may contain buffer and flash memories having different address systems from each other. Each memory chip may...
8205031 Memory management system and method thereof  
The invention discloses a memory management system and a memory management method are disclosed. The memory management system includes a first memory, at least one secondary memory, and a memory...
8200884 Reconfigurable memory module and method  
A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory...
8200883 Micro-tile memory interfaces  
In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage...
8200882 Memory system, access control method therefor, and computer program  
A memory system includes: a memory that has plural banks; a memory controller that includes a request queue and a bank monitor and controls access to the memory; a master group including plural...
8194265 Method of authenticating content provided to image forming apparatus and image forming apparatus to perform the method  
A method of authenticating at least one piece of content provided to an image forming apparatus in which at least one consumable is disposed includes determining whether the at least one...
8195906 Method and system for cascaded flashcopy zoning and algorithm and/or computer program code and method implementing the same  
A method of performing cascaded flashcopy (FC) including starting a flashcopy map when a target disk is already a source of an active FC map. A computer storage system includes a configuration...
8190808 Memory device having staggered memory operations  
A memory system includes logical banks divided into sub-banks or collections of sub-banks. The memory system responds to memory-access requests (e.g., read and write) directed to a given logical...