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8533397 Improving performance in a cache mechanism by way of destaging data in partial strides  
A method for improving performance in a storage system is provided. The method comprises receiving a request to destage a partial stride of data from a storage cache; reserving space for a full...
8527836 Rank-specific cyclic redundancy check  
Embodiments of the present disclosure describe methods, apparatus, and system configurations for providing rank-specific cyclic redundancy checks in memory systems.
8527676 Reducing latency in serializer-deserializer links  
A system for increasing the efficiency of data transfer through a serializer-deserializer (SerDes) link, and for reducing data latency caused by differences between arrival times of the data on...
8520758 Multicarrier digital signal transmission system using filter banks and memory preloading for initialization  
A transmission system includes an emitter (100) that includes an iFFT block (101) coupled to a set of memories (102-105) feeding a weighted summation device (106). Switches (113, 114, 115) are...
8510612 Disabling outbound drivers for a last memory buffer on a memory channel  
Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory...
8510370 Array-based distributed storage system with parity  
In one general aspect, a data access method is disclosed that includes directing data block write requests from different clients to different data storage servers based on a map. Data blocks...
8510496 Scheduling access requests for a multi-bank low-latency random read memory device  
Method and apparatus for scheduling access requests for a multi-bank low-latency random read memory (LLRRM) device within a storage system. The LLRRM device comprising a plurality of memory banks,...
8505013 Reducing data read latency in a network communications processor architecture  
Described embodiments provide address translation for data stored in at least one shared memory of a network processor. A processing module of the network processor generates tasks corresponding...
RE44402 System and method for storing a sequential data stream  
The present invention provides an improved apparatus and method for the receipt of high-speed sequential data streams. It utilizes the concept of banked memories to reduce the required speed and...
8483061 Technique for performing layer 2 processing using a distributed memory architecture  
A distributed memory architecture for a layer 2 processing circuit chip (50) is described. In one implementation, the layer 2 processing circuit chip (50) comprises an external memory interface...
8484404 Digital signal processing architecture supporting efficient coding of memory access information  
A digital signal processing architecture supporting efficient coding of memory access information is provided. In an example embodiment, a digital signal processor includes an adjustment value...
8477383 Processing based on command and register  
An image processing apparatus that applies image processing to image data read from a memory, the image processing apparatus including: an image processing input circuit that acquires a command...
RE44342 Bus architecture employing varying width uni-directional command bus  
A processor-memory bus comprises a command portion for transmitting addresses and commands, having a unidirectional input portion for transmitting commands to a central repeater unit, and a...
8468421 Memory system for error checking fetch and store data  
A memory system is provided. The memory system includes a memory element that is configured to selectively output data stored to and data fetched from the memory element. An error checking station...
8468298 Management device and management method  
Timing at which a rotation of a physical disk can stop is taken to more appropriately stop the rotation of the physical disk. A management device for managing a storage device and a server...
8463986 Memory system and method of controlling memory system  
A plurality of free-block management lists for respectively managing a logical block with a same bank number, a same chip number, and a same plane number as a free block, and a free block...
8463979 Non-volatile storage devices, methods of addressing, and control logic therefor  
Non-volatile storage devices and methods capable of achieving large capacity solid state drives containing multiple banks of memory devices. The storage devices include a printed circuit board, at...
8452911 Synchronized maintenance operations in a multi-bank storage system  
A method and system for managing maintenance operations in a multi-bank non-volatile storage device is disclosed. The method includes receiving a data write command and associated data from a host...
8447911 Unordered load/store queue  
A method and processor for providing full load/store queue functionality to an unordered load/store queue for a processor with out-of-order execution. Load and store instructions are inserted in a...
8441671 Dynamic module configuration in a controller area network (CAN) with fixed sub-module board identification and plug-N-play support  
According to aspects of the embodiments, there is provided methods and systems for configuring modules and sub-modules in a control area network (CAN) of a printer system using machine data and...
8443162 Methods and apparatus for dynamically managing banked memory  
Techniques for controllably allocating a portion of a plurality of memory banks as cache memory are disclosed. To this end, a configuration tracker and a bank selector are employed. The...
8438328 Emulation of abstracted DIMMs using abstracted DRAMs  
One embodiment of the present invention sets forth an abstracted memory subsystem comprising abstracted memories, which each may be configured to present memory-related characteristics onto a...
8438434 N-way parallel turbo decoder architecture  
Various embodiments relate to a memory device in a turbo decoder and a related method for allocating data into the memory device. Different communications standards use data blocks of varying...
8438329 System and method for optimizing interconnections of components in a multichip memory module  
An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have approximately the same propagation time...
8432766 Multi-column addressing mode memory system including an integrated circuit memory device  
A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit...
8429367 Systems, methods and apparatuses for clock enable (CKE) coordination  
Embodiments of the invention are generally directed to systems, methods, and apparatuses for clock enable (CKE) coordination. In some embodiments, a memory controller includes logic to predict...
8429356 Write data mask method and system  
A method and system for performing byte-writes are described, where byte-writes involve writing only particular bytes of a multiple byte write operation. Embodiments include mask data that...
8429340 Storage system comprising flash memory modules subject to plural types of wear-leveling processes  
A storage system uses a plurality of flash memory modules and a storage controller. Each of the plurality of flash memory modules comprises a memory controller and at least one flash memory chip....
8423739 Apparatus, system, and method for relocating logical array hot spots  
An apparatus, system, and method are disclosed for relocating logical array hot spots. An organization module organizes a plurality of logical arrays. Each logical array comprises a plurality of...
8417870 System and method of increasing addressable memory space on a memory board  
A load-reducing memory module includes a plurality of memory components such as DRAMs. The memory components are organized into sets or ranks such that they can be accessed simultaneously for the...
8417871 System for increasing storage media performance  
A storage access system provides consistent memory access times for storage media with inconsistent access latency and reduces bottlenecks caused by the variable time delays during memory write...
8412906 Memory apparatus supporting multiple width configurations  
Described are memory apparatus organized in memory subsections and including configurable routing to support multiple data-width configurations. Relatively narrow width configurations load fewer...
8407395 Scalable memory system  
A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign....
8407394 System and methods for memory expansion  
This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes detecting a memory command directed to a logical rand and a number...
8407377 Storage system with multicast DMA and unified address space  
A system and method for clients, a control module, and storage modules to participate in a unified address space in order to and read and write data efficiently using direct-memory access. The...
8402199 Memory management system and method thereof  
The invention discloses a memory management system and a memory management method are disclosed. The memory management system includes a first memory, at least one secondary memory, and a memory...
8402232 Memory utilization tracking  
A hardware memory control unit that includes a register block and hardware logic. The register block includes, for a hardware memory segment, an access count register, a low threshold register,...
8397011 Scalable mass data storage device  
A scalable data storage device which includes non-volatile memory uses a networked bus system which can be employed on a single memory storage chip level or in a multi-chip package (MCP). The...
8397010 Convenient, flexible, and efficient management of memory space and bandwidth  
A device may receive a request to read data from or write data to a memory that includes a number of memory banks. The request may include an address. The device may perform a mapping operation on...
8392689 Address optimized buffer transfer requests  
In one embodiment, a data storage device comprises a buffer, a buffer manager, and a buffer client. The buffer client is configured to receive data to be stored in the buffer, to compute a...
8386693 Information processing device and information processing method  
In an information processing device for processing VLIW includes memory banks, a memory banks are used to store an instruction word group constituting a very-long instruction. A program counter...
8386706 Method and system for secure data storage  
A method and system for secure data storage and retrieval is provided. A sequence of data units is divided into multiple subsets of data units corresponding to multiple data channels. The multiple...
8386739 Writing to memory using shared address buses  
Techniques for writing to memory using shared address buses. A memory device that includes a plurality of memory arrays connected to a common address bus, the common address bus used to broadcast...
8380940 Multi-channel multi-port memory  
A multi-channel multi-port memory is disclosed. In a particular embodiment, the multi-channel memory includes a plurality of channels responsive to a plurality of memory controllers. The...
8380674 System and method for migrating lun data between data containers  
A system and method for lun migration between data containers, such as aggregates of a storage system is provided. A new destination lun is created on a destination aggregate. A background copy...
8375259 System and method for initializing a memory system, and memory device and processor-based system using same  
Systems, controllers, and methods are disclosed, such as an initialization system including a controller configured to receive patterns of read data coupled from a memory device through a...
8370558 Apparatus and method to merge and align data from distributed memory controllers  
We describe a system and method to merge and align data from distributed memory controllers. A memory system includes a command bus to transmit a predetermined memory access command, and a memory...
8370557 Pseudo dual-port SRAM and a shared memory switch using multiple memory banks and a sideband memory  
A memory is described which includes a main memory array made up of multiple single-ported memory banks connected by parallel read and write buses, and a sideband memory equivalent to a single...
8364916 Method and apparatus for implementing interleaving and de-interleaving at second time  
A method for second interleaving is disclosed. The method comprises: generating an interleaving address preset in an interleaving matrix for each input data, and writing the data into the...
8364881 Flash memory controller and methods of programming and reading flash memory devices using the controller  
A system including a plurality of NAND flash memory devices each having a NAND flash interface, where the NAND flash interface of each NAND flash memory device includes an 8-bit data bus, and a...