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8688891 Memory controller, method of controlling unaligned memory access, and computing apparatus incorporating memory controller  
A computing apparatus for accessing a multiple bank memory is provided. The computing apparatus includes a processor, a memory and a memory controller which is configured to store data in a data...
8688962 Gather cache architecture  
Apparatuses and methods to perform gather instructions are presented. In one embodiment, an apparatus comprises a gather logic module which includes a gather logic unit to identify locality of...
8677051 Memory system, control method thereof, and information processing apparatus  
According to the embodiment, a nonvolatile semiconductor memory that includes a plurality of banks capable of operating in parallel, a command analyzing unit that, upon receiving a power...
8671252 Scalable memory system  
A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign....
8661180 Memory controlling device and memory controlling method  
Disclosed herein is a memory controlling device including: an address converting section configured to convert a logical address included in a request issued from a plurality of clients into a...
8661187 System, method, and computer program product for skewing expected wearout times of memory devices  
A method in one embodiment includes writing first data to a first memory device of a memory array at a first number of writes per unit time; writing second data to a second memory device of the...
8661224 Wirelessly configurable memory device addressing  
A memory device includes a plurality of memory modules and a memory management module. A memory module of the plurality of memory modules includes a plurality of memory cells and a memory...
8656116 Integrating plurality of processors with shared memory on the same circuit based semiconductor  
A shared memory made on a chip based on semiconductors comprising: an integer number m, greater than one, of data buses; m address and control buses; m input/output interfaces, each input/output...
8650655 Information processing apparatus and information processing program  
According to one embodiment, there is provided a an information processing apparatus, including: a program acceptance portion; a program storage portion; a first function type storage portion; a...
8645610 Organizing and managing a memory blade with super pages and buffers  
A system and method is illustrated wherein a protocol agent module receives a memory request encoded with a protocol, the memory request identifying an address location in a memory module managed...
8645609 Two-port memory implemented with single-port memory blocks  
A two-port memory having a read port, a write port and a plurality of identical single-port RAM banks. The capacity of one of the single-port RAM banks is used to resolve collisions between...
8639894 Efficient read and write operations  
Computer readable media, methods and apparatuses are disclosed that may be configured for sequentially reading data of a file stored on a storage medium. The disclosure also provides for...
8639891 Method of operating data storage device and device thereof  
The method of operating the data storage device includes performing channel distribution non-sequentially based on a logical address included in a data signal and outputting a channel address, and...
8634486 Signal receiving apparatus, signal receiving method and signal receiving program  
A signal receiving apparatus includes: a processing unit configured to carry out Fourier transform on Fourier-transform data serving as a Fourier-transform object and carry out Fourier transform...
8635394 Method, an interface for volatile and non-volatile memory devices as well as a related computer program product, and a device  
Accessing data stored in a memory device through an interface, with addressing data on the memory device through at least one address bus, controlling at least data flow to and from the memory...
8635390 System and method for a hierarchical buffer system for a shared data bus  
The present invention provides a system and method for controlling data entries in a hierarchical buffer system. The system includes an integrated circuit device comprising: a memory core, a...
8635393 Semiconductor memory having a short effective word line cycle time and method for reading data from a semiconductor memory of this type  
The invention relates to a method for reading data from a semiconductor memory, said method comprising the following steps in this order: providing at least one first memory bank and at least one...
8631193 Emulation of abstracted DIMMS using abstracted DRAMS  
One embodiment of the present invention sets forth an abstracted memory subsystem comprising abstracted memories, which each may be configured to present memory related characteristics onto a...
8631211 Disk drive diagnosis apparatus  
According to an aspect of an embodiment, a disk drive diagnosis apparatus is included in a RAID system in which a RAID control unit and a drive enclosure that encloses a disk drive are...
8631220 Adjusting the timing of signals associated with a memory system  
A system and method are provided for adjusting the timing of signals associated with a memory system. A memory controller is provided. Additionally, at least one memory module is provided....
8627003 Apparatus, system, and method for memory upgrade path optimization  
An apparatus, system, and method are disclosed for memory upgrade optimization. A requirements module 402 receives one or more of a capacity upgrade goal 1306 for an overall capacity of the array...
8626997 Phase change memory in a dual inline memory module  
Subject matter disclosed herein relates to management of a memory device.
8626998 Multi-rank memory module that emulates a memory module having a different number of ranks  
A transparent four rank memory module has a front side and a back side. The front side has a third memory rank stacked on a first memory rank. The back side has a fourth memory rank stacked on a...
8627022 Contention free parallel access system and a method for contention free parallel access to a group of memory banks  
A parallel access system including: a group of processing entities that comprises N processing entities; wherein N is a positive integer that exceeds one; a group of memory banks that stores K...
8621135 Semiconductor memory device and information data processing apparatus including the same  
A semiconductor memory device includes a plural number of data input/output pins, a plural number of banks, in each of which a plural number of the information data is stored, a selector and a...
8621137 Metadata rebuild in a flash memory controller following a loss of power  
A method of rebuilding metadata in a flash memory controller following a loss of power. The method includes reading logical address information associated with an area of flash memory, and using...
8621132 System and methods for memory expansion  
This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving first initialization data from a physical dual inline...
8612664 Memory management process and apparatus for the same  
Memory management process for optimizing the access to a central memory located within a processing system comprising a set of specific units communicating with each other through said memory,...
8607022 Processing quality-of-service (QoS) information of memory transactions  
Systems and methods for processing quality-of-service (QoS) information of memory transactions are described. In an embodiment, a method comprises receiving identification information and...
8601332 Systems and methods for monitoring a memory system  
Systems and methods are disclosed herein, including those that operate to monitor a first set of operational parameters associated with a memory vault, to adjust a second set of operational...
8601200 Controller for solid state disk which controls access to memory bank  
A controller for a solid state disk is provided. The controller includes a storage module to store an index of at least one idle bank among a plurality of memory banks, and a control module to...
8595420 Method for dispatching and transmitting data streams between host system and memory storage apparatus having non-volatile memory and smart card chip, memory controller, and memory storage apparatus  
A data stream dispatching method for a memory storage apparatus having a non-volatile memory module and a smart card chip is provided. The method includes configuring a plurality of logical block...
8593866 Systems and methods for operating multi-bank nonvolatile memory  
A non-volatile memory system that has multiple memory banks initially assigns logical addresses to memory banks according to an assignment scheme, maintains this assignment for a period of time,...
8589615 System and method for DRAM bank assignment  
A network device includes memory having memory banks, and a packet processor module configured to receive bursts of packets and segment a received packet into a plurality of sections corresponding...
8583873 Multiport data cache apparatus and method of controlling the same  
A multiport data cache apparatus and a method of controlling the same are provided. The multiport data cache apparatus includes a plurality of cache banks configured to share a cache line, and a...
8583851 Convenient, flexible, and efficient management of memory space and bandwidth  
A device may receive a request to read data from or write data to a memory that includes a number of memory banks. The request may include an address. The device may perform a mapping operation on...
8570764 Backplane and backplane communication system  
The embodiments of the present invention disclose a backplane and backplane system. The backplane includes at least two service slots with the same function and an exchange slot. Among the pins of...
8566560 System and method for configuring storage resources for database storage  
A system and method for configuring storage resources for database storage are disclosed. A method may include mapping at least one first tablespace having a first block size to at least one first...
8560756 Hybrid flash memory device  
A hybrid memory system is provided that combines the advantages of NAND flash memory devices with the advantages of NOR flashes memory devices. The system includes a NAND flash memory portion to...
8559451 Turbo decoder  
A turbo decoder has at least two Bahl, Cocke, Jelinek, and Raviv (BCJR) processors in parallel, each in serial communication with respective interleavers. The BCJR processors and interleavers are...
8560795 Memory arrangement for multi-processor systems including a memory queue  
A hardware memory architecture or arrangement suited for multi-processor systems or arrays is disclosed. In one aspect, the memory arrangement includes at least one memory queue between a...
8560757 System and method to reduce memory access latencies using selective replication across multiple memory ports  
In one embodiment, a system includes memory ports distributed into subsets identified by a subset index, where each memory port has an individual wait time based on a respective workload. The...
8554963 Storage system with multicast DMA and unified address space  
A system and method for clients, a control module, and storage modules to participate in a unified address space in order to and read and write data efficiently using direct-memory access. The...
8554982 Storage device and information processing system  
A storage device able to make a redundant write operation of unselected data unnecessary and able to optimize an arrangement of pages to a state having a high efficiency for rewriting, wherein the...
8549209 Bridging device having a configurable virtual page size  
A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. The bridge device has memory organized as banks, where each bank is...
8549342 Method and apparatus for fine edge control on integrated circuit outputs  
A device for adjusting the timing of at least one edge of an output pulse created in response to a reference pulse is disclosed. Such a device may include a first memory circuit having two or more...
8539136 Techniques for dynamic disk personalization  
Techniques for dynamic disk personalization are provided. A virtual image that is used to create an instance of a virtual machine (VM) is altered so that disk access operations are intercepted...
8539174 Use by a host device having a first file system of a portable storage device having a second file system and supporting file segmentation  
A host device includes a first file system, and a storage device includes a plurality of memory units and a plurality of controllers. While the host device is operative coupled to the storage...
8539143 Memory systems and methods of initiallizing the same  
A memory system is provided includes a host processor, and a plurality of cascade connected memory cards connected to the host processor. Each of the memory cards stores a same default relative...
8539196 Hierarchical organization of large memory blocks  
A multi-bank memory system includes one or more levels of logical memory hierarchy to increase the available random cyclic transaction rate of the memory system. The memory system includes a...