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7404047 |
Method and apparatus to improve multi-CPU system performance for accesses to memory
Methods and apparatuses for improving processor performance in a multi-processor system by optimizing accesses to memory. Processors can track the state of a memory such that the memory can be...
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7404060 |
Apparatus, program, and method for managing usage of memory
A memory management apparatus suitable for reducing amount of memory usage and simplifying programs is provided. When an area allocation request has been inputted, an unused area having a size that...
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7404048 |
Inter-cluster communication module using the memory access network
An inter-cluster communication module using the memory access network is provided, including a plurality of clusters, a memory subsystem, a controller and a switch device. When some clusters issue...
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7401124 |
Apparatus and method to write information to two geographically separated virtual tape servers
A method to write information to two geographically separated virtual tape servers, where the method provides a file to a virtual tape controller, writes that file to a first virtual tape server,...
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7401176 |
Method and system for fast access to stack memory
Fast access of a memory having a stack uses an address bit, a stack pointer, and fast access random access memory (“RAM”). When a first address mode is used in conjunction with the address bit...
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7401169 |
Counter updating system using an update mechanism and different counter utilization mechanism
Disclosed are, inter alia, methods, apparatus, data structures, computer-readable media, and mechanisms for maintaining counters, such as in, but not limited to a packet switching system, and...
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7401177 |
Data storage device, data storage control apparatus, data storage control method, and data storage control program
A data storage device includes a memory including a plurality of memory banks, a data storage processor that initially arranges data in the plurality of memory banks based on an access pattern...
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7392339 |
Partial bank DRAM precharge
A “partial PRECHARGE command” is used to precharge a fraction of the banks in a multi-bank DRAM. In a first implementation the command precharges one half of the banks. In a second...
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7389387 |
Distributed memory module cache writeback
One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at...
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7386651 |
System, method, and apparatus for efficiently storing macroblocks
Presented herein is a system for storing macroblocks for such that all vertically, horizontally, and diagonally adjacent macroblock are stored in different banks. When fetching a block from a...
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7386596 |
High performance storage access environment
The present invention provides improved techniques for managing storage resources, such as disk drives, I/O ports, and the like in a network based storage system according to a user position within...
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7383416 |
Method for setting a second rank address from a first rank address in a memory module
A method for setting an address of a rank in a memory module having a number of memory chips distributed along a byte lane includes setting the first memory chip of the byte lane to have a first...
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7380048 |
System and method for managing data in memory for reducing power consumption
A system or method to partition data in a memory based at least in part to a data type, and to refresh the memory based at least in part to the data type.
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7373453 |
Method and apparatus of interleaving memory bank in multi-layer bus system
A method and apparatus of interleaving memory banks in a multi-layer bus system. The apparatus includes a plurality of slave interface units receiving signals requesting a bus access and generating...
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7370161 |
Bank arbiter system which grants access based on the count of access requests
Provided are an arbiter capable of improving memory access efficiency in a multi-bank memory, a memory access arbitration system including the arbiter, and an arbitration method thereof, where the...
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7366821 |
High-speed memory system
A memory system has a memory controller and a plurality of memories. The plurality of memories are connected via a switch to an end of a bus, which is connected to the memory controller, wherein...
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7366820 |
Second-cache driving/controlling circuit, second cache, RAM, and second-cache driving/controlling method
A circuit for driving and controlling a second cache that is incorporated in a processor and comprises a plurality of RAM. The circuit comprises a second-cache control unit 1 A and a chip-enable...
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7366822 |
Semiconductor memory device capable of reading and writing data at the same time
A semiconductor memory device includes a plurality of banks. A data path may be divided into a read data path and a write data path, therefore, parallel processing of write and read commands are...
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7366827 |
Method and apparatus for selectively transmitting command signal and address signal
A method for transmitting a command signal and an address signal to a rank which is to be accessed includes receiving and buffering the command signal and the address signal, and transmitting the...
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7363458 |
Computer platform memory configuration on-board indicating method and system
A computer platform memory configuration on-board indicating method and system is proposed, which is designed for use with a computer platform, such as a network server, for providing a memory...
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7363452 |
Pipelined burst memory access
A memory device for multichannel continuous or fixed burst mode operation includes multiple burst address counter circuits and associated control logic to minimize latency which would otherwise...
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7363419 |
Method and system for terminating write commands in a hub-based memory system
A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub....
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7360038 |
Storage control system and method
A storage control system comprises a first controller connected through a first access route to a first storage; a second controller connected through a second access route to a second storage...
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7360040 |
Interleaver for iterative decoder
Interleaver for iterative decoder. A memory management scheme allows for single plane/single port memory devices to be used by the interleaver. The design is adaptable to soft-in soft-out (SISO)...
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7353319 |
Method and apparatus for segregating shared and non-shared data in cache memory banks
In a multiprocessor system, accesses to a given processor's banked cache are controlled such that shared data accesses are directed to one or more banks designated for holding shared data and/or...
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7353322 |
System and method for providing dynamic configuration ROM using double image buffers
A dynamic configuration ROM which may be updated while linked to the serial bus and with little or no risk of publishing inconsistent configuration ROM information to the other nodes on the bus....
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7353357 |
Apparatus and method for pipelined memory operations
A semiconductor memory device has a memory core that includes at least eight banks of dynamic random access storage cells and an internal data bus coupled to the memory core. The internal data bus...
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7353328 |
Memory testing
A memory subsystem may be usable in an electronic system. The memory subsystem may comprise a memory controller and a plurality of memory modules coupled to the memory controller. The memory module...
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7346750 |
Memory interleave system
A memory interleave system includes M (M=2 p , where p is a natural number) memory banks, M memory control units (MCU) corresponding respectively to the M memory banks, N (a natural number) CPUs,...
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7345901 |
Computer system having daisy chained self timed memory chips
A computer system having a memory system, the memory system having a memory controller and a memory. The memory comprises one or more daisy chains of self timed memory chips. An address/command...
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7346731 |
High performance and scalable width expansion architecture for fully parallel CAMs
A technique that provides highly scalable width expansion architecture for cascading CAMs to facilitate searching of increased wordlengths. In one example embodiment, this is achieved by combining...
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7343444 |
Reconfigurable memory module and method
A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory...
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7343443 |
Updated package generation based on analysis of bank dependency
Aspects of the present invention may be seen in an electronic device network that employs a generator to generate update packages and a corresponding update agent in the electronic device to update...
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7343457 |
Dual active bank memory controller
A memory controller for managing memory requests from a plurality of requesters to a plurality of memory banks is disclosed. The memory controller includes an arbiter, a first path controller, a...
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7340558 |
Multisection memory bank system
A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and...
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7337265 |
Organization of cache memory for hardware acceleration of the finite-difference time-domain method
Disclosed herein is an organization of cache memory for hardware acceleration of the FDTD method. The organization of cache memory for hardware acceleration of the FDTD method provides a...
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7336098 |
High speed memory modules utilizing on-pin capacitors
Apparatus and method for producing memory modules having a plurality of branches connected to a memory bus, each branch containing at least one dynamic random access memory (DRAM) device or SDRAM...
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7337266 |
Data structure design system and method for prolonging the life of an FRAM
A data structure design system for prolonging the life of an FRAM (Ferroelectric Random Access Memory) includes a CPU (Central Processing Unit) ( 1 ), an FRAM ( 2 ), an SDRAM (Synchronous Dynamic...
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7330954 |
Storing information in one of at least two storage devices based on a storage parameter and an attribute of the storage devices
Briefly, in accordance with an embodiment of the invention, a method to store information is provided, wherein the method includes generating a storage parameter to store information, wherein the...
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7328314 |
Multiprocessor computing device having shared program memory
An instruction memory shared by a number of processing units has a plurality of individually accessible sections. A software program in the instruction memory is distributed among the memory...
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7321950 |
Method and apparatus for managing write-to-read turnarounds in an early read after write memory system
A method and apparatus for managing write-to-read turnarounds in an early read after write memory system are presented. Memory controller logic identifies a write operation's bank set, allows a...
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7321949 |
Memory device including self-ID information
Disclosed is a memory device including self-ID information. The memory device has a storage unit for storing information related to the memory device, such as a manufacturing factory, a...
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7320048 |
Apparatus and method to switch a FIFO between strobe sources
A first-in, first-out (FIFO) unit switches between strobe sources. The FIFO uses a multiplexer to switch between two or more strobes so that different data strobes may be used with the FIFO to...
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7318114 |
System and method for dynamic memory interleaving and de-interleaving
In one embodiment, a system includes a plurality of memory controllers each coupled between a processor and a respective memory. Each memory controller includes a plurality of decoders. Each...
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7318115 |
IC memory complex with controller for clusters of memory blocks I/O multiplexed using collar logic
Method and apparatus for reducing power consumption in a digital specific signal processor integrated circuit. Data buses are routed through multiplexers to reduce the number of busses routed...
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7313645 |
Processor to reduce data rearrangement instructions for matrices in multiple memory banks
The present invention provides a processor including: a plurality of memory banks; a read-address generation circuit for supplying a read address to each of the memory banks on the basis of a...
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7307453 |
Method and system for parallel state machine implementation
Methods and computer readable media are provided for implementing state machines in parallel. A control vector is generated from current state and input bits. This vector is then used to determine...
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7308524 |
Memory chain
A memory system having a plurality of memory devices and a memory controller. The memory devices are coupled to one another in a chain. The memory controller is coupled to the chain and configured...
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7305516 |
Multi-port memory device with precharge control
There is provided a multi-port memory device, which is capable of preventing a first high data fail phenomenon at an initial operation in a current sensing type global data bus...
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7302620 |
Interleaving.deinterleaving device and method for communication system
A device for sequentially storing input bit symbols of a given interleaver size N in a memory at an address from 0 to N−1 and reading the stored bit symbols from the memory. The device comprises...
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