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7519788 |
System and method for an asynchronous data buffer having buffer write and read pointers
A system and method for facilitating the adjustment of timing parameters between a memory controller operating in a first clock domain and a memory device operating in a second clock domain. A...
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7519762 |
Method and apparatus for selective DRAM precharge
Apparatus and method for using a precharge command in which a plurality of address lines are individually used to specify which banks of memory cells within a memory device have an open row that is...
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7519696 |
Method and apparatus for dynamically modifying a computer system configuration
One embodiment is directed to a method and apparatus for modifying a configuration of a computer system including a host computer and at least one computer system resource accessible to at least...
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7516264 |
Programmable bank/timer address folding in memory devices
A set of N copies of bank control logic are provided for tracking the banks within the memory modules (DRAMS). When the total number of banks within the memory module(s) is greater than N, the...
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7516282 |
Control device and control method for memory
A control device for a memory is provided. The control device includes a micro-control unit (MCU), a command queue, a command sequencer, and a table. The control device is coupled to the memory and...
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7512847 |
Method for estimating and reporting the life expectancy of flash-disk memory
A method for managing a memory device, a memory device so managed and a system that includes such a memory device. A value of a longevity parameter of the device is monitored after a data operation...
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7508706 |
Nonvolatile semiconductor memory device provided with data register for temporarily holding data in memory array
A precharge signal generation circuit outputs a precharge signal including a pulse every access cycle with respect to a data register in a first mode, and generates a precharge signal by masking...
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7509302 |
Device, method and program for providing a high-performance storage access environment while issuing a volume access request including an address of a volume to access
The present invention provides a high-performance storage access environment to a user who moves around a wide area, while increasing the fault resistance of the system. A plurality of network...
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7505356 |
Multi-column addressing mode memory system including an integrated circuit memory device
A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit...
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7506130 |
Mirrored computer memory on split bus
A fully mirrored memory system includes at least one split memory bus, with each portion of the split memory bus having active memory and mirror memory. Each portion of the memory bus transfers a...
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7499954 |
Consistent reintegration of a failed primary instance
A method and system are provided for providing a consistent reintegration of a failed primary instance as a new secondary instance with implementation of truncation of log records. Upon failure of...
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7496777 |
Power throttling in a memory system
A memory system is disclosed. The memory system includes a memory controller coupled to one or more memory modules, at least one of the memory modules including a buffer. The memory controller is...
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7493441 |
Mass storage controller with apparatus and method for extending battery backup time by selectively providing battery power to volatile memory banks not storing critical data
A battery-backed write-caching mass storage controller is disclosed. The controller includes a plurality of volatile memory banks for caching write data prior to being written to disk drives....
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7493457 |
States encoding in multi-bit flash cells for optimizing error rate
To store N bits of M≧2 logical pages, the bits are interleaved and the interleaved bits are programmed to ┌N/M┐ memory cells, M bits per cell. Preferably, the interleaving puts the same...
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7493469 |
Performance evaluation apparatus, performance evaluation method, program and computer readable recording medium
From an application program described in the form of a flow graph, input and output arcs are extracted. Packet rates on the input and output arcs are extracted, and it is determined whether the...
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7489571 |
Semiconductor device for switching a defective memory cell bit of data to replacement data on the output data line
A semiconductor device is provided for outputting data read from a read only storage device. The semiconductor device includes a read only storage device including memory cells, an address signal...
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7490190 |
Method and system for local memory addressing in single instruction, multiple data computer system
A single instruction, multiple data (“SIMD”) computer system includes a central control unit coupled to 256 processing elements (“PEs”) and to 32 static random access memory (“SRAM”)...
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7490217 |
Design structure for selecting memory busses according to physical memory organization information stored in virtual address translation tables
Design structures for program directed memory access patterns. A design structure is embodied in a machine readable storage medium used in a design process, the design structure including a...
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7487301 |
Method and system for accelerated access to a memory
Method of transferring data between a memory comprising several banks and a data processing circuit, the method comprising the steps of:
producing access requests ( 46, 47 ) defining each...
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7487318 |
Managing write-to-read turnarounds in an early read after write memory system
Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read...
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7480781 |
Apparatus and method to merge and align data from distributed memory controllers
We describe a system and method to merge and align data from distributed memory controllers. A memory system includes a command bus to transmit a predetermined memory access command, and a memory...
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7480759 |
System, method and storage medium for providing data caching and data compression in a memory subsystem
A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory...
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7478213 |
Off-chip micro control and interface in a multichip integrated memory system
A communication interface, coupling a controller device to one or more memory devices, provides a high-voltage reset interface. The high-voltage reset interface provides a high-voltage signal to...
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7475259 |
Multiple nonvolatile memories
One or more embodiments of the invention provide a method, apparatus, and article of manufacture for preventing unauthorized access to digital services comprising. Access control to digital...
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7475205 |
System for inventory control of an automated data storage library
An automated data library system employing a plurality of cartridges, one or more cartridge storage slots and an inventory controller. Each cartridge includes a cartridge memory. The cartridge...
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7472255 |
Method for addressing a symbol in a memory and device for processing symbols
A bitwise addressing mode includes including the shaping of symbols of variable length during an operation for reading or writing a symbol in a bank of memories. The addressing is then done with...
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7467139 |
Library lock management
An apparatus for and method of permitting the maintenance/control console of a large scale mainframe computer to list the contents of program libraries in the demand or even batch mode with minimum...
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7460545 |
Enhanced SDRAM bandwidth usage and memory management for TDM traffic
A method and apparatus for managing memory for time division multiplexed high speed data traffic is provided. The method and apparatus utilize an interleaving approach in association with multiple...
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7457937 |
Method and system for implementing low overhead memory access in transpose operations
Embodiments of the present invention recite a method and system for accessing data. In one embodiment of the present invention, a plurality of instances of data are stored in a memory device which...
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7453752 |
Method for hiding a refresh in a pseudo-static memory with plural DRAM sub-arrays and an on-board address decoder
A method and device for hiding refresh operations during accesses to sub-arrays of a pseudo-static memory device. By refreshing sub-array j while filling the row R i (where i≠j) corresponding...
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7454555 |
Apparatus and method including a memory device having multiple sets of memory banks with duplicated data emulating a fast access time, fixed latency memory device
An apparatus includes two multi-bank memory devices for storing duplicate data in each memory bank in an embodiment of the invention. The two memory devices are able to replace a more expensive...
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7451282 |
System and method for storing a sequential data stream
The present invention provides an improved apparatus and method for the receipt of high-speed sequential data streams. It utilizes the concept of banked memories to reduce the required speed and...
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7447830 |
Information processing system and memory controller for controlling operation of memories
An information processing system includes a plurality of memories grouped into a first memory group and a second memory group, a data processor transmitting a data access request to the memories,...
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7444458 |
Method for assigning addresses to memory devices
A memory system having a memory controller and several separate memory devices connected to the controller by a system bus. The memory devices each included an array of memory cells, addressing...
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7437571 |
Dedicated nonvolatile memory
One or more embodiments of the invention provide a method, apparatus, and article of manufacture for limiting unauthorized access to digital services. A protected nonvolatile memory component is...
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7436728 |
Fast random access DRAM management method including a method of comparing the address and suspending and storing requests
A method to manage fast random access of a DRAM memory is described. The method includes steps of: dividing the memory into memory banks accessible independently in read and write mode; identifying...
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7433429 |
De-interleaver method and system
In one embodiment, interleaved signals in a receiver are accessed by memory pointers and delivered to data stream locations without the need to transfer data to an intermediate physical buffer.
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7433992 |
Command controlling different operations in different chips
In some embodiments, the invention includes a chip having a register to include an operation type signal. The chip also includes control circuitry to receive a first command and in response to the...
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7426603 |
Memory bus arbitration using memory bank readiness
A method, apparatus, and computer program product includes identifying a plurality of memory transactions to be sent over a memory bus to a memory having a plurality of memory banks, each memory...
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7424573 |
Information processing apparatus, method, and program for formatting multiple recording media integrated as one
An information processing apparatus reads and writes information in a plurality of recording media is provided. The apparatus includes a formatting determination section which, in the case of...
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7421564 |
Incrementing successive write operations to a plurality of memory devices
A centralized memory allocation system utilizes write pointer drift correction. The memory stores data units. The memory controller receives a write request associated with a data unit and stores...
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7418540 |
Memory controller with command queue look-ahead
In general, in one aspect, the disclosure describes accessing multiple memory access commands from a one of multiple memory access command queues associated with, respective, banks of a Random...
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7417883 |
I/O data interconnect reuse as repeater
Some embodiments may include a memory with a first memory device and data pins, and a second memory device coupled with some of the data pins of the first memory device, allowing the first memory...
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7415567 |
Memory hub bypass circuit and method
A computer system and a method used to access data from a plurality of memory devices with a memory hub. The computer system includes a plurality of memory modules coupled to a memory hub...
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7415565 |
Methods and systems for a storage system with a program-controlled switch for routing data
A storage system that may include one or more memory devices, a memory interface device corresponding to one or more of the memory devices, which are organized in sections, a section controller,...
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7409492 |
Storage system using flash memory modules logically grouped for wear-leveling and RAID
A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory...
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7406564 |
Distributed FIFO
Circuits, methods, and apparatus for FIFO memories made up of multiple local memory arrays. These embodiments limit the number and length of interconnect lines that are necessary to join two or...
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7404050 |
Method of operating a memory device, memory module, and a memory device comprising the memory module
There is provided a method of operating a memory device comprising at least one memory module, a corresponding memory module and a memory device comprising the at least one memory module. It is...
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7404057 |
System and method for enhancing read performance of a memory storage system including fully buffered dual in-line memory modules
A system and method for enhanced read performance of a memory storage system is disclosed. The storage system includes a first memory controller. At least one first channel of a plurality of memory...
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7404036 |
Rebalancing of striped disk data
Provided are a method, system, and article of manufacture, where a plurality of extents are stored in a first set of storage units coupled to a controller. A determination is made that a second set...
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