Match Document Document Title
8850100 Interleaving codeword portions between multiple planes and/or dies of a flash memory device  
A system, a method and a non-transitory computer readable medium are disclosed. The non-transitory computer readable medium may store instructions for: (I) interleaving at least two portions of a...
8843723 Multi-dimension memory timing tuner  
In embodiments of a multi-dimension memory timing tuner, a memory device controller that can be interfaced with one or more memory devices is coupled to a memory device for data communication with...
8838873 Methods and apparatus for data access by a reprogrammable circuit module  
In some embodiments, an apparatus includes a set of memory modules configured to store data and a reprogrammable circuit module operatively coupled to the set of memory modules. The reprogrammable...
8832350 Method and apparatus for efficient memory bank utilization in multi-threaded packet processors  
A method and apparatus for efficient memory bank utilization in multi-threaded packet processors is presented. A plurality of memory access requests, are received and are buffered by a plurality...
8825965 System and methods for memory expansion  
This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving a memory request from a memory controller over a channel....
8819304 Storage system with multicast DMA and unified address space  
A system and method for clients, a control module, and storage modules to participate in a unifed address space in order to and read and write data efficiently using direct-memory access. The...
8819359 Hybrid interleaving in memory modules by interleaving physical addresses for a page across ranks in a memory module  
A memory system that interleaves storage of data across and within a plurality memory modules is described. The memory system includes a hybrid interleaving mechanism which maps physical addresses...
8817033 Method and apparatus for performing adaptive memory bank addressing  
A display system comprises a mapping memory comprising a plurality of memory banks configured to store a plurality of image tiles corresponding to an image, and an image mapping component...
8819379 Allocating memory based on performance ranking  
A method for optimizing memory bandwidth using bank-based memory allocation is described. The method includes receiving a request for an allocation of memory. In response to receiving the request,...
8806103 System and method for interleaving memory  
One system may comprise an interleave system that determines a desired interleave for at least a selected portion of a distributed memory system. A migration system is associated with the...
8806132 Information processing device, memory access control device, and address generation method thereof  
An information processing device according to the present invention includes an operation unit that outputs an access request, a storage unit including a plurality of connection ports and a...
8799553 Memory controller mapping on-the-fly  
Systems, methods, and devices for dynamically mapping and remapping memory when a portion of memory is activated or deactivated are provided. In accordance with an embodiment, an electronic device...
8799552 Microcontroller with special banking instructions  
An instruction set for a microcontroller with a data memory divided into a plurality of memory banks wherein the data memory has more than one memory bank of the plurality of memory banks that...
8793445 Method and system for improved deskewing of data  
Embodiments of the present invention are directed to a method, computer-readable medium and system for deskewing data. More specifically, skewed data is accessed and written into a plurality of...
8793426 Microcontroller with linear memory access in a banked memory  
A microcontroller has a data memory divided into a plurality of memory banks, an address multiplexer for providing an address to the data memory, an instruction register providing a first partial...
8788745 Storage system comprising flash memory modules subject to two wear—leveling processes  
A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory...
8775747 Write data mask method and system  
A method and system for performing byte-writes are described, where byte-writes involve writing only particular bytes of a multiple byte write operation. Embodiments include mask data that...
8775717 Storage controller for flash memory including a crossbar switch connecting a plurality of processors with a plurality of internal memories  
A controller designed for use with a flash memory storage module, including a crossbar switch designed to connect a plurality of internal processors with various internal resources, including a...
8773883 System and memory module  
A system includes: a controller, a first memory module connected to the controller through a first data bus, and a second memory module connected to the controller through a second data bus,...
8775686 Transactional memory that performs an atomic metering command  
A transactional memory (TM) receives an Atomic Metering Command (AMC) across a bus from a processor. The command includes a memory address and a meter pair indicator value. In response to the AMC,...
8769241 Virtualization of non-volatile memory and hard disk drive as a single logical drive  
Systems and techniques relating to storage technologies are described. A described technique includes operating drives such as a solid state drive (SSD) and a disk drive, where the SSD and the...
8769239 Re-mapping memory transactions  
Systems and methods for re-mapping memory transactions are described. In an embodiment, a method includes receiving a memory request from a hardware subsystem to a memory, replacing a first...
8769234 Memory modules and devices supporting configurable data widths  
Described are memory apparatus organized in physical banks and including configurable data control circuit to support multiple data-width configurations. Relatively narrow width configurations...
8762620 Multiprocessor storage controller  
A storage controller containing multiple processors. The processors are divided into groups, each of which handles a different stage of a pipelined process of performing host reads and writes. In...
8756394 Multi-dimension memory timing tuner  
In embodiments of a multi-dimension memory timing tuner, a memory device controller that can be interfaced with one or more memory devices is coupled to a memory device for data communication with...
8756364 Multirank DDR memory modual with load reduction  
A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The memory module...
8756363 Efficient storage of memory version data  
Systems and methods for efficient memory corruption detection in a processor. A processor detects a first data structure is to be allocated in a physical memory. The physical memory may be a DRAM...
8756381 Storage subsystem and load distribution method for executing data processing using normal resources even if an abnormality occurs in part of the data processing resources that intermediate data processing between a host computer and a storage device  
A storage subsystem coupled to a host computer is described. The storage subsystem includes storage devices and first and second storage apparatuses that control data transfer between the host...
8756362 Methods and systems for determining a cache address  
A method and system are provided for determining a next available address for writing data to a cache memory. In one implementation, a method includes receiving a request for a candidate address...
8751723 Memory access control device, method and recording medium for simultaneously accessing horizontally or vertically consecutive unit data or unit data on vertically alternate lines in different modes  
An access control device, which increases memory access efficiency to data stored in a memory, includes a plurality of groups of the memory, and divides and stores the data in different memory...
8751860 Object oriented memory in solid state devices  
The present disclosure includes methods, devices, and systems for object oriented memory in solid state devices. One embodiment of a method for object oriented memory in solid state devices...
8751769 Efficient address generation for pruned interleavers and de-interleavers  
Techniques for efficiently generating addresses for pruned interleavers and pruned de-interleavers are described. In an aspect, a linear address may be mapped to an interleaved address for a...
8751755 Mass storage controller volatile memory containing metadata related to flash memory storage  
A volatile memory associated with a mass storage controller and a flash memory module. The volatile memory includes a number of tables containing information related to the flash memory storage,...
8745464 Rank-specific cyclic redundancy check  
Embodiments of the present disclosure describe methods, apparatus, and system configurations for providing rank-specific cyclic redundancy checks in memory systems.
8745319 Flash memory based storage devices utilizing magnetoresistive random access memory (MRAM) to store control information facilitating wear leveling  
A flash memory based storage device may utilize magnetoresistive random access memory (MRAM) as at least one of a device memory, a buffer, or high write volume storage. In some embodiments, a...
8745312 Storage device and method of mapping a nonvolatile memory based on a map history  
A non-volatile memory may include a plurality of map blocks for storing a plurality of map units, the map units representing mapping information between physical addresses and logical addresses. A...
8745355 Method for assigning addresses to memory devices  
A memory system having a memory controller and several separate memory devices connected to the controller by a system bus. The memory devices each included an array of memory cells, addressing...
8738840 Operating system based DRAM/FLASH management scheme  
A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory...
8738841 Flash memory controller and system including data pipelines incorporating multiple buffers  
A storage controller connected to a flash memory storage module, the controller and module including multiple sets of buffers. The buffers are part of one or more pipelines through which data is...
8732382 Haltable and restartable DMA engine  
A method is described for operation of a DMA engine. Copying is initiated for transfer of a first number of bytes from first source memory locations to first destination memory locations. Then, a...
8732383 Reconfigurable memory module and method  
A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory...
8725943 Method and system for secure data storage  
A method and system for secure data storage and retrieval is provided. A sequence of data units is divided into multiple subsets of data units corresponding to multiple data channels. The multiple...
8719519 Split-word memory  
Method, process, and apparatus to efficiently store, read, and/or process syllables of word data. A portion of a data word, which includes multiple syllables, may be read by a computer processor....
8706999 Method and system for cascaded flashcopy zoning and algorithm and/or computer program code and method implementing the same  
A method of performing cascaded flashcopy (FC) including starting a flashcopy map when a target disk is already a source of an active FC map. A computer storage system includes a configuration...
8706945 Memory control device  
To provide a technology of increasing the number of ranks of a memory module with a small change in architecture. A memory control device accessing a memory module having a plurality of ranks,...
8699277 Memory configured to provide simultaneous read/write access to multiple banks  
A memory includes at least first and second banks of single-port memory elements, a first local controller adapted to send read and write instructions to the first memory bank, and a second local...
8700838 Allocating heaps in NUMA systems  
Processes may be assigned heap memory within locally accessible memory banks in a multiple processor NUMA architecture system. A process scheduler may deploy a process on a specific processor and...
8694750 Method and system for data structure management  
Embodiments of the present invention are directed to a method and system for allowing data structures to be moved between storage locations of varying performance and cost without changing the...
8694970 Unified debug system with multiple user-configurable trace volumes and trace buffers  
A unified debug system with multiple user-configurable trace volumes is disclosed, including embodiments as a system, a method, and a computer-readable medium. Embodiments of the present invention...
8688892 System and method for increasing DDR memory bandwidth in DDR SDRAM modules  
A system and method for increasing DDR memory bandwidth in DDR SDRAM modules are provided. DDR memory has an inherent feature called the Variable Early Read command, where the read command is...