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7017002 System featuring a master device, a buffer device and a plurality of integrated circuit memory devices  
A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device...
7010656 Method and apparatus for memory management  
In some embodiments, an electronic device includes a processor, a physical memory coupled to the processor, and a storage medium coupled to the processor. The storage medium may store instructions...
7010654 Methods and systems for re-ordering commands to access memory  
Methods and systems for re-ordering commands to access memory are disclosed. Embodiments may receive a first command to access a memory bank of the memory and determine a penalty associated with...
7010642 System featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices  
A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device...
7007130 Memory system including a memory module having a memory module controller interfacing between a system memory controller and memory devices of the memory module  
A system that has a system memory controller and a memory module. The memory module includes a memory module controller coupled to the system memory controller and a plurality of memory devices...
7003622 Semiconductor memory  
A semiconductor memory includes a redundant RAM disposed independently of at least one regular RAM, the redundant RAM having redundant memory elements by which defective memory elements of the...
7003640 Power-aware adaptation in an information server  
An information server with power-aware adaptation that enables power reduction while minimizing the performance impact of power reduction. An information server according to the present techniques...
7003630 Mechanism for proxy management of multiprocessor storage hierarchies  
A method and apparatus within a processing environment is provided for proxy management of a plurality of proxy caches connected to a plurality of processing elements or cores within a unified...
7003639 Memory controller with power management logic  
A memory controller controls access to, and the power state of a plurality of dynamic memory devices. A cache in the memory controller stores entries that indicate a current power state for a...
7003618 System featuring memory modules that include an integrated circuit buffer devices  
A computer system includes a controller device having an interface disposed on a circuit board. A first socket is disposed on the circuit board and receives a first memory module having a first...
7000089 Address assignment to transaction for serialization  
The assignment of an address to a transaction for serialization purposes is disclosed. A simulated address is assigned to a transaction of a first type. The simulated address may be determined by...
7000062 System and method featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices  
A system comprises a master device and a first integrated circuit buffer device. A first plurality of integrated circuit memory devices are coupled to the first integrated circuit buffer device. A...
6996607 Storage subsystem and method employing load balancing  
A storage subsystem that directly interfaces with a network, provides connections for routers with a conventional multi-path function, and performs access load balancing among a plurality of...
6993637 Unified memory system for multiple processors and method for controlling the same  
A memory system for multiple processors includes a unified memory including a plurality of memory banks, and a memory controller coupled to the unified memory. The memory controller receives...
6990640 DIMM and method for producing a DIMM  
A method for producing a DIMM having a reduced memory capacity. The method includes determining an amount by which a memory capacity of a DIMM can be reduced, and reducing the memory capacity of...
6986081 Block interleaving apparatus, block deinterleaving apparatus, block interleaving method and block deinterleaving method  
In a block interleaving apparatus, a block deinterleaving apparatus, a block interleaving method, and a block deinterleaving method for performing block interleaving and block deinterleaving by...
6985992 Wear-leveling in non-volatile storage systems  
Methods and apparatus for performing wear leveling in a non-volatile memory system are disclosed. According to one aspect of the present invention, a method for allocating non-volatile memory that...
6981122 Method and system for providing a contiguous memory address space  
A memory system and a method for operating a memory system are provided. The memory system includes a set of memory banks, logic for calculating a first address in each memory bank from the set of...
6976145 Method and apparatus for automatically configuring data storage subsystems  
A method and apparatus are disclosed in a data processing system for automatically replicating a first data storage subsystem's configuration data on a second data storage subsystem. Storage...
6970968 Memory module controller for providing an interface between a system memory controller and a plurality of memory devices on a memory module  
A memory module controller for providing interface between a system memory controller and a plurality of memory devices on a memory module. The memory module includes first interface circuitry and...
6968419 Memory module having a memory module controller controlling memory transactions for a plurality of memory devices  
A memory module that has a plurality of memory devices and a memory module controller configured to receive a memory transaction from a first memory bus and to control access to the plurality of...
6968440 Systems and methods for processor memory allocation  
In one embodiment, there is disclosed a system and method for mapping memory addresses to system memory by establishing the size and location of each memory rank within the system memory,...
6968402 System and method for storing chunks of first cache line and second cache line in a buffer in a first and second chunk order  
Techniques to buffer and present chunks are disclosed. In some embodiments, a first interface may receive chunks of a first cache line, and a second interface may receive chunks of a second cache...
6965969 Non-uniform cache apparatus, systems, and methods  
An apparatus or system may comprises cache control circuitry coupled to a processor, and a plurality of independently accessible memory banks (228) coupled to the cache control circuitry. Some of...
6965980 Multi-sequence burst accessing for SDRAM  
Methods and apparatus for accessing memory locations in a memory device in different orders. In one implementation, a memory device includes: a memory array, including a plurality of memory...
6959256 Universally accessible fully programmable memory built-in self-test (MBIST) system and method  
A universally accessible fully programmable memory built-in self-test (MBIST) system including an MBIST controller having an address generator configured to generate addresses for a memory under...
6957310 Interleave address generation device and interleave address generation method  
Counter control section 101 increments a row number and column number on a two-dimensional array for a block interleave expressed by a matrix two-dimensional array, outputs the incremented numbers...
6954822 Techniques to map cache data to memory arrays  
Methods and apparatuses for mapping cache contents to memory arrays. In one embodiment, an apparatus includes a processor portion and a cache controller that maps the cache ways to memory banks....
6954837 Consolidation of allocated memory to reduce power consumption  
A memory system includes physical memory devices or ranks of memory devices that can be set to reduced power modes. In one embodiment, a hardware memory controller receives memory instructions in...
6952752 File memory device and information processing apparatus using the same  
A flash memory based file memory device built in an information processing apparatus enables fast file access. The file memory device is provided with a parallel arrangement of memory element...
6950920 Dual controller system for dynamically allocating control of disk units  
A disk array system of the type that each controller has an independent and dedicated cache. The disk array system can change control of a desired volume between desired controllers without...
6948046 Access controller that efficiently accesses synchronous semiconductor memory device  
An SDRAM access control section activates a row of an SDRAM when a request is made to access the row in the continuous access mode. The SDRAM access control section outputs a read command or a...
6948044 Methods and apparatus for storage virtualization  
Methods and apparatus are provided improving data access efficiency in a storage area network. Mechanisms are provided to allow a virtual disk address to be efficiently mapped to a particular...
6948030 FIFO memory system and method  
A FIFO memory system for multiple input channels, has a channel control logic coupled to a channel input signal. A pointer and flag logic block is coupled to an output of the channel control...
6944739 Register bank  
A filter register bank, for example, for a CAN module provides parallel and serial access. The filter bank comprises a plurality of memory cells arranged in a matrix of columns and rows, wherein...
6944731 Dynamic random access memory system with bank conflict avoidance feature  
A memory system having multiple memory banks is configured to prevent bank conflict between access requests. The memory system includes a memory controller and a plurality of memory banks...
6941416 Apparatus and methods for dedicated command port in memory controllers  
A memory controller includes a chip-select-interface controller and a synchronous random-access-memory (SDRAM)-interface controller. The chip-select-interface controller communicates with a...
6938129 Distributed memory module cache  
One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at...
6937247 Memory control device and method  
A memory control device and a method of controlling memory transfer. The memory control device has a command decoding device, a compare logic device, a decision device, a frame buffer decode...
6931505 Distributed memory module cache command formatting  
One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at...
6931498 Status register architecture for flexible read-while-write device  
A single status register, capable of providing status for simultaneous read-while-write operation on a flash memory array is described. The status of the memory array is reported to the user based...
6931479 Method and apparatus for multi-functional inputs of a memory device  
A memory device having multi-functional input terminals to provide greater flexibility without adding new input terminals. The memory device takes advantage of input terminals of a memory device...
6930903 Arrangement of integrated circuits in a memory module  
Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of 1-Gigabyte and 2-Gigabyte capacity memory modules. A first row of...
6931507 Memory allocation method using multi-level partition  
The present invention relates to a memory allocation method using multi-level partition, which is capable of analyzing an allocation-requested fixed size to be used as a basic allocation unit,...
6928459 Plurality of file systems using weighted allocation to allocate space on one or more storage devices  
Space is allocated on storage devices in proportion to weights associated with the storage devices. The space is allocated by a plurality of file systems. In particular, space may be allocated on...
6925543 Burst transfer memory  
The present invention provides a burst transfer memory comprising a first memory having a cell array arranged in a matrix, a second memory which has a cell array arranged in a matrix and which...
6922770 Memory controller providing dynamic arbitration of memory commands  
Embodiments of the present invention provide a memory controller comprising a front-end module, a back-end module communicatively coupled to the front-end module, and a physical interface module...
6922758 Synchronous flash memory with concurrent write and read operation  
A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication...
6920523 Bank address mapping according to bank retention time in dynamic random access memories  
A system and method for refreshing data in a dynamic random access memory (“DRAM”) is provided, where the system includes a data memory having a plurality of memory banks, a map memory in signal...
6920522 Synchronous flash memory with accessible page during write  
A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication...