Match Document Document Title
7136978 System and method for using dynamic random access memory and flash memory  
A system and method are provided for using dynamic random access memory and flash memory. In one example, the memory system comprises a nonvolatile memory; synchronous dynamic random access...
7137023 Auxiliary alarm clock system for a personal computer  
The present invention provides systems and methods to operate a PC as an alarm clock. An IC is provided to monitor the power status of PC and generate an alarm clock event at a preselected time....
7133962 Circulator chain memory command and address bus topology  
Embodiments of the invention provide a memory command and address (CA) bus architecture that can accommodate higher CA data output frequencies with reduced signal degradation. For one embodiment...
7133960 Logical to physical address mapping of chip selects  
In some embodiments, a system and method for mapping the logical chip selects to a physical chip select. A chip select remapping unit receives logical chip select associated with a dual in-line...
7133959 Data-driven information processing device and method to access multiple bank memories according to multiple addresses  
An address calculation unit calculates a plurality of addresses corresponding to a plurality of data included in a data packet. A first bank memory access unit accesses a first bank memory...
7130967 Method and system for supplier-based memory speculation in a memory subsystem of a data processing system  
A data processing system includes one or more processing cores, a system memory having multiple rows of data storage, and a memory controller that controls access to the system memory and performs...
7130229 Interleaved mirrored memory systems  
In some embodiments, a system includes a first memory assembly coupled to a first channel and a second memory assembly coupled to a second channel. The system includes a memory controller to write...
7127564 Double buffered flash programming  
A double buffered flash bank. In one embodiment, a flash interface may be programmed by a register interface with a first set of data while a second set of data is being written to the register...
7126873 Method and system for expanding flash storage device capacity  
Through the use of an allocation logic unit with a Flash controller, a single primary chip enable is de-multiplexed into a multiple secondary chip enables for multiple Flash memory dies or chips....
7127547 Processor with multiple linked list storage feature  
A processor includes controller circuitry operative to control the storage of a plurality of separate linked list data structures for protocol data units received by the processor. The linked list...
7124263 Memory controller, semiconductor integrated circuit, and method for controlling a memory  
A memory controller includes a state generator configured to generate a plurality of state information signals in response to command requests associated with a plurality of banks in a memory. An...
7120077 Memory module having a plurality of integrated memory components  
A memory module includes a plurality of integrated memory components are arranged on a mounting substrate and a refresh control circuit arranged separately from the memory components on the...
7120727 Reconfigurable memory module and method  
A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory...
7117291 Memory with synchronous bank architecture  
In a synchronous multi-port bank memory, registers/buffers receive a read/write signal and an address signal from each of external ports, receive and send a data signal to and from each of the...
7117307 Memory controlling apparatus performing the writing of data using address line  
A memory controlling apparatus which receives from an upper module of a system a command to read data from a memory module or write data in the memory module and controls accessing the memory...
7114012 Computer system and method for migrating from one storage system to another  
The present invention provides a method for migrating from a source storage system to a target storage system. The method comprises the steps of: defining a volume defined on a drive to be...
7111107 Microcontroller with dedicated memory bank for servicing interrupts  
A microcontroller with expandable memory banks has a microprocessor, a plurality of memory banks with only one page for storing interrupt service routines(ISR), a memory bank control circuit...
7110321 Multi-bank integrated circuit memory devices having high-speed memory access timing  
Integrated circuit memory devices support write and read burst modes of operation with uniformly short interconnect paths that provide high-speed memory access timing characteristics. These memory...
7107412 Distributed processor memory module and method  
A memory module for a computer system is removably coupled to a computer system mother-board having a data bus and an address bus. The memory module includes a memory interface, a program memory...
7107386 Memory bus arbitration using memory bank readiness  
A method, apparatus, and computer program product includes identifying a plurality of memory transactions to be sent over a memory bus to a memory having a plurality of memory banks, each memory...
7099989 System and technique to reduce cycle time by performing column redundancy checks during a delay to accommodate variations in timing of a data strobe signal  
A memory device includes a memory cell array, an addressing circuit, a data communication circuit and a control circuit. The addressing circuit receives first signals that are indicative of an...
7099988 Apparatus and method to read information from an information storage medium  
A method to read (N) sequential files written to an information storage medium, and then skip the next (M) sequential files. The method initially identifies the (M) files to be skipped. After...
7093059 Read-write switching method for a memory controller  
A system includes a memory device. The memory device has a first bank and a second bank. A memory controller has a write request queue to store write requests. When a read bank conflict exists...
7089558 Inter-partition message passing method, system and program product for throughput measurement in a partitioned processing environment  
A partitioned processing system is disclosed wherein a workload calculation is implemented for at least one partition. CPU utilization and I/O throughput information is used in calculating...
7089379 Large high bandwidth memory system  
A memory system is divided into memory subsystems. Each subsystem includes a slave controller. Each slave controller is coupled to a serial link. A master controller is coupled to the slave...
7080193 Flash memory with accessible page during write  
A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication...
7076618 Memory controllers with interleaved mirrored memory modes  
In some embodiments, a memory controller includes first and second memory channel interfaces and memory access control circuitry. The memory access control circuitry is to send first and second...
7076617 Adaptive page management  
Machine-readable media, methods, and apparatus are described which process memory transactions. In some embodiments, a memory controller of a processor and/or chipset may adaptively determine...
7073014 Synchronous non-volatile memory system  
A computer system comprises a memory controller and a synchronous non-volatile memory device coupled to the memory controller via a main memory bus. The synchronous non-volatile memory device has...
7072986 System and method for displaying storage system topology  
A management display method according to each type of interfaces and devices is provided in an environment where host computers are interconnected with storage apparatuses through plural types of...
7073012 System and method for interleaving data in a communications device  
A system and method is provided for interleaving data in a communications device. The system includes a memory for storing symbols of a data block, a read module and a write module, each of which...
7065608 Apparatus for recording data and method for writing data to flash memory  
The present invention provides an apparatus for recording data, including a storage unit (4) for reading out management information stored in the flash memory (2) to store read out management...
7062630 Storing device for writing data onto a plurality of installed storing mediums, storing control method for the storing device, and program thereof  
A storing device can reduce the frequency of the saving operation at a step of rewriting data on the storing mediums. Where q is a size of all the data to write in storing mediums, m is the number...
7058756 Circuit for implementing special mode in packet-based semiconductor memory device  
Disclosed is a circuit for implementing a special mode in a packet-based semiconductor memory device, which performs the special mode in the same manner as a normal operation without changing the...
7055012 Latency reduction using negative clock edge and read flags  
A method of selecting CAS latencies in a system. Specifically, a system which includes a plurality of memory devices and a memory controller is provided. Because different memory devices may have...
7051171 Method and system for providing a multi-channel interleaver/deinterleaver using SDRAM  
A deinterleaver for performing high-speed multi-channel forward error correction using external SDRAM is provided. According to one exemplary aspect, the deinterleaver performs both read and write...
7047385 High-speed memory for use in networking systems  
A memory integrated circuit includes an array of high-speed memory blocks coupled to the address input interface and data output interface of the integrated circuit by address and data pipelines...
7047371 Integrated memory having a memory cell array containing a plurality of memory banks, and circuit configuration having an integrated memory  
An integrated memory has at least two connection panels, which can be operated independently of one another, for external communication by the memory. In addition, a control circuit produces a...
7043598 Method and apparatus for dynamic memory refreshing  
In a memory device with a bank of N memory blocks, an address is generated for a first and a second one of the blocks. The first and second addresses include addresses for current first and second...
7043617 System supporting multiple memory modes including a burst extended data out mode  
A system is capable of receiving Fast Page mode, Extended Data Out mode, Burst Extended Data Out mode, or a combination of these memory devices. A method of determining the type of memory present...
7038964 Access to a common memory in which a priority access to a non-active bank is prepared during a non-priority access to a different bank  
Access of multiple data processing circuits to a common memory having several banks is managed, the memory being connected to one or several circuits for processing ordinary data and to a circuit...
7035161 Semiconductor integrated circuit  
An I/O interface circuit immediately close to a bank having a plurality of memory cells and an I/O circuit is directly connected to data line pairs via a switching circuit. Another I/O interface...
7035962 Pipelined packet-oriented memory system having a unidirectional command and address bus and a bidirectional data bus  
A memory system having at least one memory subsystem and using a packet protocol communicated over a command and address bus and at least one data bus. The memory subsystems are pipelined to...
7028135 Multiple partition memory command user interface  
A multiple partition memory array has a command user interface for each partition, and a logic interface. The logic interface receives signals from each of the command user interfaces to restrict...
7028209 I2C repeater with voltage translation  
A bus repeater with voltage conversion and multiplexing circuits for use between devices with incompatible voltage levels communicating over inter-integrated circuit (I2C) buses. Bi-directional...
7024578 Array of synchronized memory modules  
A memory apparatus includes a memory module array having several memory modules. Each memory module has a synchronization connection for receiving a synchronization signal for synchronizing the...
7024515 Methods and apparatus for performing continue actions using an associative memory which might be particularly useful for implementing access control list and quality of service features  
Methods and apparatus are disclosed for use with an associative memory, such as for, but not limited to implementing access control list and quality of service features in a communications or...
7020736 Method and apparatus for sharing memory space across mutliple processing units  
A method and apparatus for sharing memory space of multiple memory units by multiple processing units are described. In an embodiment, a method includes storing a set of data across more than one...
7020758 Context sensitive storage management  
The invention relates to methods and associated systems for managing application workloads and data storage resources. Data storage resources my be mapped to logical addresses associated with...
7020757 Providing an arrangement of memory devices to enable high-speed data access  
A memory subsystem includes multiple memory modules coupled by point-to-point links. A memory controller is coupled by a point-to-point link to a first memory module, which is turn is coupled by...