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7257670 Multipurpose CAM circuit  
A content addressable memory (CAM) device for use in various sizes of systems while requiring minimal circuitry to enlarge the size of the prioritization circuitry. In smaller systems, the CAM...
7243183 SONET data byte switch  
A switch system including a plurality of input ports and a plurality of output ports for transferring data from one of the input ports to one of the output ports, and a plurality of memory devices...
7240145 Memory module having a memory controller to interface with a system bus  
A memory module includes a memory module controller to be coupled to a system memory controller by a system memory bus and a plurality of memory devices coupled to the memory module controller,...
7240144 Arbitration of data transfer requests  
A data processor core 10 comprising: a memory access interface portion 30 operable to perform data transfer operations between an external data source and at least one memory 120 associated with...
7239563 Semiconductor device for outputting data read from a read only storage device  
A semiconductor device for outputting data read from a read only storage device, includes a plurality of read only storage devices, each including memory cells, a plurality of selecting signal...
7233612 Wireless communication deinterleaver using multi-phase logic and cascaded deinterleaving  
A deinterleaver module in an OFDM wireless transceiver includes partitioned memory banks for storage of code word fragments from an interleaved data stream, each code word fragment associated with...
7234019 Method and apparatus for implementing a search engine using an SRAM  
A search engine system including a memory bank coupled to a bank selection signal, mask logic for receiving constructed keys and incoming key masks and for providing masked keys, hash function...
7228393 Memory interleaving  
A central processor unit (CPU) accesses memory to read and write data and to read and execute program instructions. A problem arises when accessing slower Flash or electrically programmable read...
7225306 Efficient address generation for Forney's modular periodic interleavers  
An efficient way to generate the address sequence for the RAM implementation of Forney's (P, D, m) interleavers requires only A+1+2P memory locations, which is close to the theoretical minimum....
7222224 System and method for improving performance in computer memory systems supporting multiple memory access latencies  
A memory system having multiple memory devices reduces average access latency by enabling different latencies for different regions of physical memory, providing an address map conducive to...
7219184 Method and apparatus for longest prefix matching in processing a forwarding information database  
A hardware circuit implemented on a DRAM foundry is provided for finding the longest prefix key match. The hardware circuit includes the use of prefix search engines to store prefix keys. Each...
7219200 Method of accessing matrix data with address translation circuit that enables quick serial access in row or column directions  
A method of accessing matrix data of a semiconductor memory having memory banks. The memory banks each having memory cells arranged in X and Y directions, a Y decoder for selecting Y-direction...
7219185 Apparatus and method for selecting instructions for execution based on bank prediction of a multi-bank cache  
A processor having the capability to dispatch multiple parallel operations, including multiple load operations, accesses a cache which is divided into banks. Each bank supports a limited number of...
7216212 Semiconductor memory with self-refresh capability  
A memory device comprises a plurality of banks of storage locations accessible in response to access requests. Data refresh means are provided for refreshing data stored in the storage locations...
7215561 Semiconductor memory system having multiple system data buses  
The semiconductor memory system includes a memory controller, N system data buses, and first through P-th memory module groups. The N system data buses are connected to the memory controller and...
7216202 Method and apparatus for supporting one or more servers on a single semiconductor chip  
One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During operation, the system allows a process to...
7212307 Image data storage system  
A CPU determines whether the intended use of the image data to be stored in a plurality of HDDs has a first-type purpose, which requires storing temporarily stored image data for carrying out...
7213099 Method and apparatus utilizing non-uniformly distributed DRAM configurations and to detect in-range memory address matches  
Methods, software and systems to determine channel ownership and physical block location within the channel in non-uniformly distributed DRAM configurations and also to detect in-range memory...
7213102 Apparatus method and system for alternate control of a RAID array  
Secondary or augmented control of a storage array in a cost effective manner is accomplished by connecting a host to the storage array via a storage adapter independent of a RAID controller. The...
7210002 System and method for operating dual bank read-while-write flash  
The disclosed embodiments provide for a system and method for storing data in a flash memory device that has a code bank and a data bank. The method includes writing data to the data bank under...
7210030 Programmable memory initialization system and method  
The present invention provides for a system for programmable memory initialization. A configuration module is configured with initialization control commands and associated configuration...
7206860 Virtualization switch and storage system  
A virtualization switch virtualizes a data storage area provided by a server device and provides it to a server device. This virtualization switch processes a priority control and a bandwidth...
7206863 System and method for managing storage networks and providing virtualization of resources in such a network  
This invention is a system and method for managing one or more data storage networks using a new architecture. A method for handling logical to physical mapping is included in one embodiment with...
7206918 Address predicting apparatus and methods  
Apparatus and methods for addressing predicting useful in high-performance computing systems. The present invention provides novel correlation prediction tables. In one embodiment, correlation...
7203794 Destructive-read random access memory system buffered with destructive-read memory cache  
A memory storage system includes a plurality of memory storage banks and a cache in communication therewith. Both the plurality of memory storage banks and the cache further include destructive...
7203818 Microcontroller instruction set  
A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space...
7197607 Non-volatile memory with concurrent write and read operation to differing banks  
A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication...
7194572 Memory system and method to reduce reflection and signal degradation  
Embodiments of the invention provide a memory command and address (CA) bus architecture that can accommodate higher CA data output frequencies with reduced signal degradation. For one embodiment...
7194568 System and method for dynamic mirror-bank addressing  
A dynamic addressing technique mirrors data across multiple banks of a memory resource. Information stored in the memory banks is organized into separately addressable blocks, and memory addresses...
7191295 Sensing word groups in a memory  
In one embodiment of the present invention, a method includes sensing a first burst length of data equal to half of a sense width of a plurality of sense amplifiers of a memory, and sensing a...
7185159 Technique for accessing memory in a data processing apparatus  
The present invention provides a data processing apparatus and method for accessing memory. The data processing apparatus has a secure domain and a non-secure domain, in the secure domain the data...
7185139 Easy access port structure and access method  
The present invention provides an easy access ports structure. In accordance with the present invention, each port has a register bank. Each register bank has the same address. A global register...
7181563 FIFO memory with single port memory modules for allowing simultaneous read and write operations  
The present invention is directed to a FIFO memory with single port memory modules that may allow simultaneous read and write operations. In an exemplary aspect of the present invention, a method...
7174415 Specialized memory device  
A specialized memory chip which includes an embedded application specific signal processing unit ASSPU. The ASSPU handles one or more predetermined tasks instead of a main processing unit. The...
7171529 Single-chip microcomputer with read clock generating circuits disposed in close proximity to memory macros  
Flash ROMs operate at a speed slower than that of a CPU. In order to raise the operating speed of a single-chip microcomputer, therefore, interleaving is adopted and a plurality of flash ROMs are...
7167967 Memory module and memory-assist module  
A computer body outputting a predetermined number of address signals A0 to A11 and a plurality of select signals CSO and CSI, generates a memory select signal CS and an additional address signal...
7167942 Dynamic random access memory controller  
An apparatus, and method and computer program thereof, comprises a plurality of ports each adapted to receive packets of data; a memory controller core adapted to generate one or more memory...
7162608 Translation lookaside buffer-based memory system and method for use in a computer having a plurality of processor element  
A system and method for addressing memory and transferring data, which in some embodiments include one or more processor translation look-aside buffers (TLBs) and optionally one or more I/O TLBs,...
7162591 Processor memory having a dedicated port  
Methods and apparatus are provided for closely coupling a dedicated memory port to a processor core while allowing external components access to the dedicated memory. A processor core such as a...
7162568 Apparatus and method for flash ROM management  
An apparatus and method of flash ROM management. The apparatus comprises a storage device, a strapping component and a process unit. The storage device stores multiple address records comprising...
7159067 Information processing apparatus using index and TAG addresses for cache  
In an information processing apparatus involving a cache accessed by INDEX and TAG addresses, accesses to the main memory include many accesses attributable to the local character of referencing...
7159066 Precharge suggestion  
Machine-readable media, methods, and apparatus are described which process memory transactions. In some embodiments, a processor requests an external memory controller to close a storage location...
7151683 High speed memory modules utilizing on-trace capacitors  
Apparatus and method for producing memory modules having a plurality of dynamic random access memory (DRAM) devices or synchronous random access memory (SDRAM) devices connected to a memory bus,...
7149842 Efficient utilization of shared buffer memory and method for operating the same  
Broadly speaking, an apparatus for efficiently utilizing a shared packet buffer memory in a switch and a method for operating the same is provided. More specifically, the apparatus includes a...
7149827 Methods and apparatus for tristate line sharing  
Methods and apparatus are provided for interconnecting on-chip components, such as components on a programmable chip, with off-chip components through a variety of buses, fabrics, and input/output...
7143236 Persistent volatile memory fault tracking using entries in the non-volatile memory of a fault storage unit  
One embodiment disclosed relates to a method for persistently tracking volatile memory faults. A memory error is detected in relation to at least one dynamic random access memory (DRAM) unit on a...
7143207 Data accumulation between data path having redrive circuit and memory device  
Memory apparatus and methods accumulate data between a data path and a memory device. A memory agent may have a data accumulator between a redrive circuit and a memory device or interface. The...
7143185 Method and apparatus for accessing external memories  
A network switch that controls the communication of data frames between stations includes receive devices that correspond to ports on the network switch. The receive devices receive and store data...
7139862 Interleaving method and apparatus with parallel access in linear and interleaved order  
An interleaving method and apparatus provides parallel access in a linear and interleaved order to a predetermined number of stored data samples. A memory array with a plurality of memory devices...
7140023 Symbolic buffer allocation in local cache at a network processing element  
According to some embodiments, a portion of local memory allocated to a thread by a programming statement includes an indication of a read/write status of the portion and symbolically references a...