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7353328 Memory testing  
A memory subsystem may be usable in an electronic system. The memory subsystem may comprise a memory controller and a plurality of memory modules coupled to the memory controller. The memory...
7353319 Method and apparatus for segregating shared and non-shared data in cache memory banks  
In a multiprocessor system, accesses to a given processor's banked cache are controlled such that shared data accesses are directed to one or more banks designated for holding shared data and/or...
7353322 System and method for providing dynamic configuration ROM using double image buffers  
A dynamic configuration ROM which may be updated while linked to the serial bus and with little or no risk of publishing inconsistent configuration ROM information to the other nodes on the bus....
7346750 Memory interleave system  
A memory interleave system includes M (M=2p, where p is a natural number) memory banks, M memory control units (MCU) corresponding respectively to the M memory banks, N (a natural number) CPUs,...
7346731 High performance and scalable width expansion architecture for fully parallel CAMs  
A technique that provides highly scalable width expansion architecture for cascading CAMs to facilitate searching of increased wordlengths. In one example embodiment, this is achieved by combining...
7345901 Computer system having daisy chained self timed memory chips  
A computer system having a memory system, the memory system having a memory controller and a memory. The memory comprises one or more daisy chains of self timed memory chips. An address/command...
7343457 Dual active bank memory controller  
A memory controller for managing memory requests from a plurality of requesters to a plurality of memory banks is disclosed. The memory controller includes an arbiter, a first path controller, a...
7343443 Updated package generation based on analysis of bank dependency  
Aspects of the present invention may be seen in an electronic device network that employs a generator to generate update packages and a corresponding update agent in the electronic device to...
7340558 Multisection memory bank system  
A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and...
7337266 Data structure design system and method for prolonging the life of an FRAM  
A data structure design system for prolonging the life of an FRAM (Ferroelectric Random Access Memory) includes a CPU (Central Processing Unit) (1), an FRAM (2), an SDRAM (Synchronous Dynamic...
7336098 High speed memory modules utilizing on-pin capacitors  
Apparatus and method for producing memory modules having a plurality of branches connected to a memory bus, each branch containing at least one dynamic random access memory (DRAM) device or SDRAM...
7337265 Organization of cache memory for hardware acceleration of the finite-difference time-domain method  
Disclosed herein is an organization of cache memory for hardware acceleration of the FDTD method. The organization of cache memory for hardware acceleration of the FDTD method provides a...
7330954 Storing information in one of at least two storage devices based on a storage parameter and an attribute of the storage devices  
Briefly, in accordance with an embodiment of the invention, a method to store information is provided, wherein the method includes generating a storage parameter to store information, wherein the...
7328314 Multiprocessor computing device having shared program memory  
An instruction memory shared by a number of processing units has a plurality of individually accessible sections. A software program in the instruction memory is distributed among the memory...
7321950 Method and apparatus for managing write-to-read turnarounds in an early read after write memory system  
A method and apparatus for managing write-to-read turnarounds in an early read after write memory system are presented. Memory controller logic identifies a write operation's bank set, allows a...
7321949 Memory device including self-ID information  
Disclosed is a memory device including self-ID information. The memory device has a storage unit for storing information related to the memory device, such as a manufacturing factory, a...
7320048 Apparatus and method to switch a FIFO between strobe sources  
A first-in, first-out (FIFO) unit switches between strobe sources. The FIFO uses a multiplexer to switch between two or more strobes so that different data strobes may be used with the FIFO to...
7318114 System and method for dynamic memory interleaving and de-interleaving  
In one embodiment, a system includes a plurality of memory controllers each coupled between a processor and a respective memory. Each memory controller includes a plurality of decoders. Each...
7318115 IC memory complex with controller for clusters of memory blocks I/O multiplexed using collar logic  
Method and apparatus for reducing power consumption in a digital specific signal processor integrated circuit. Data buses are routed through multiplexers to reduce the number of busses routed...
7313645 Processor to reduce data rearrangement instructions for matrices in multiple memory banks  
The present invention provides a processor including: a plurality of memory banks; a read-address generation circuit for supplying a read address to each of the memory banks on the basis of a...
7308524 Memory chain  
A memory system having a plurality of memory devices and a memory controller. The memory devices are coupled to one another in a chain. The memory controller is coupled to the chain and configured...
7307453 Method and system for parallel state machine implementation  
Methods and computer readable media are provided for implementing state machines in parallel. A control vector is generated from current state and input bits. This vector is then used to determine...
7305516 Multi-port memory device with precharge control  
There is provided a multi-port memory device, which is capable of preventing a first high data fail phenomenon at an initial operation in a current sensing type global data bus...
7302620 Interleaving.deinterleaving device and method for communication system  
A device for sequentially storing input bit symbols of a given interleaver size N in a memory at an address from 0 to N−1 and reading the stored bit symbols from the memory. The device comprises a...
7296110 Memory system and data channel initialization method for memory system  
Provided is a memory system and a method that can initialize a data channel at a high speed without the need to increase the number of pins in a semiconductor memory device, and not requiring a...
7295553 Packet buffer  
A write-bank selecting unit selects different memory banks in response to N+1 consecutive write requests, respectively. In each memory cycle, a data writing unit inputs N or less write commands to...
7293131 Access to disk storage using file attribute information  
In order to manage the various types of attribute information within the storage system, the storage system includes the following databases within a file-access controlling memory: a database for...
7290079 Device and method for small discontiguous accesses to high-density memory devices  
A memory architecture design and strategy is provided using memory devices that would normally be considered disadvantageous, but by accommodating the data input, output, and other peripheral...
7290109 Memory system and memory card  
A memory system includes a plurality of nonvolatile memory chips (CHP1 and CHP2) each having a plurality of memory banks (BNK1 and BNK2) which can perform a memory operation independent of each...
7289764 Cardholder interface for an access control system  
In a wireless access control system, a method and system for providing indications of the state of a Wireless Access Point Module (WAPM) to an observer using at least one indicator mounted on the...
7289684 Moving picture processing apparatus  
A moving picture processing apparatus in which a buffer residual amount of a buffer module which buffers a plurality of image data which are inputted from the outside is monitored by a storing...
7287119 Integrated circuit memory device with delayed write command processing  
An integrated circuit memory device having delayed write command processing includes a first set of pins coupled to a memory core, the first set of pins to receive a row address followed by a...
7287115 Multi-chip package type memory system  
A multichip package type memory system is disclosed, which comprises a plurality of types of memory integrated circuits which are provided in a memory system in a package having an internal bus,...
7281108 Method and apparatus for managing migration of data in a computer system  
Methods and apparatus for migrating a data set. In one embodiment, a migration is paused. In another embodiment, for a migration of data between multiple source/target groups, the migration is...
7281079 Method and apparatus to counter mismatched burst lengths  
Memory device having banks of memory cells organized into two groups of banks that share control circuitry and a data buffer to provide an interface to a memory bus, but which are independently...
7281081 System and method for preventing sector slipping in a storage area network  
A system for protecting a block in a destination storage device including a data mover operable to move data from a source storage device to the block, and a controller coupled to the data mover,...
7281078 Bank structure storage control device and paper matter authentication device  
A storage control device of bank structure is provided which comprises a CPU 1 and a storage 2 connected to CPU 1. Storage 2 detects and temporarily holds one of the bank addresses 0DF00h-7DF07h...
7278004 Burst write in a non-volatile memory device  
A synchronous flash memory has been described that includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The synchronous...
7278038 Operational voltage control circuit and method  
A method and apparatus for providing a preferred operating voltage to a memory device as specified by a stored configuration parameter. The apparatus includes a nonvolatile memory configured to...
7277982 DRAM access command queuing structure  
Access arbiters are used to prioritize read and write access requests to individual memory banks in DRAM memory devices, particularly fast cycle DRAMs. This serves to optimize the memory bandwidth...
7277977 DRAM for high-speed data access  
A DRAM with a general interleaving scheme for data input/output uses a normal bank structure. The DRAM provides a high-performance without consideration of a data access pattern. In order to...
7275199 Method and apparatus for a modified parity check  
A method, an apparatus, and a computer program are provided for sequentially determining parity of stored data. Because of the inherent instabilities that exist in most memory arrays, data...
7275143 System, apparatus and method for avoiding page conflicts by characterizing addresses in parallel with translations of memory addresses  
A system, apparatus, and method are disclosed for controlling accesses into memory to minimize sequential accesses to the same bank of memory, at least in part, by characterizing a subset of an...
7269684 Method and system for persistently storing objects in an object oriented environment  
A method and a system is provided for persistently storing and restoring objects of an object oriented environment established on a computer system having a volatile memory and a persistent...
7269667 Disk array system and method for migrating from one storage system to another  
A method for migrating from a source storage system to a target storage system includes defining a volume defined on a device to be migrated in the source storage system as an external volume to...
7269697 Apparatus and methodology for an input port scheduler  
A scheduler to manage the reading activity of a plurality of read hubs is described. Each read hub is capable of reading a piece of a packet from a different memory bank within a same cycle of...
7266653 Remote data mirroring with acknowledgment upon writing copied data to volatile cache memory  
A method for storing data received from a host processor at a primary storage subsystem in a data storage system includes writing the data to a first volatile cache memory in the primary storage...
7266651 Method for in-place memory interleaving and de-interleaving  
A method for in-place interleaving and de-interleaving of a memory includes, in one embodiment, generating a new address corresponding to a new location in the memory by performing a bit-wise XOR...
7266633 System and method for communicating the synchronization status of memory modules during initialization of the memory modules  
A memory system includes a memory hub controller coupled to a plurality of memory modules each of which includes a memory hub. The memory hub controller and the memory hubs each include at least...
7257665 Branch-aware FIFO for interprocessor data sharing  
A branch aware first-in first-out (FIFO) memory may include a memory array to store data; a push pointer to address memory locations therein to write data; a pop pointer to address memory...