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7475259 Multiple nonvolatile memories  
One or more embodiments of the invention provide a method, apparatus, and article of manufacture for preventing unauthorized access to digital services comprising. Access control to digital...
7475205 System for inventory control of an automated data storage library  
An automated data library system employing a plurality of cartridges, one or more cartridge storage slots and an inventory controller. Each cartridge includes a cartridge memory. The cartridge...
7472255 Method for addressing a symbol in a memory and device for processing symbols  
A bitwise addressing mode includes including the shaping of symbols of variable length during an operation for reading or writing a symbol in a bank of memories. The addressing is then done with...
7467139 Library lock management  
An apparatus for and method of permitting the maintenance/control console of a large scale mainframe computer to list the contents of program libraries in the demand or even batch mode with...
7460545 Enhanced SDRAM bandwidth usage and memory management for TDM traffic  
A method and apparatus for managing memory for time division multiplexed high speed data traffic is provided. The method and apparatus utilize an interleaving approach in association with multiple...
7457937 Method and system for implementing low overhead memory access in transpose operations  
Embodiments of the present invention recite a method and system for accessing data. In one embodiment of the present invention, a plurality of instances of data are stored in a memory device which...
7454555 Apparatus and method including a memory device having multiple sets of memory banks with duplicated data emulating a fast access time, fixed latency memory device  
An apparatus includes two multi-bank memory devices for storing duplicate data in each memory bank in an embodiment of the invention. The two memory devices are able to replace a more expensive...
7451282 System and method for storing a sequential data stream  
The present invention provides an improved apparatus and method for the receipt of high-speed sequential data streams. It utilizes the concept of banked memories to reduce the required speed and...
7447830 Information processing system and memory controller for controlling operation of memories  
An information processing system includes a plurality of memories grouped into a first memory group and a second memory group, a data processor transmitting a data access request to the memories,...
7444458 Method for assigning addresses to memory devices  
A memory system having a memory controller and several separate memory devices connected to the controller by a system bus. The memory devices each included an array of memory cells, addressing...
7437571 Dedicated nonvolatile memory  
One or more embodiments of the invention provide a method, apparatus, and article of manufacture for limiting unauthorized access to digital services. A protected nonvolatile memory component is...
7436728 Fast random access DRAM management method including a method of comparing the address and suspending and storing requests  
A method to manage fast random access of a DRAM memory is described. The method includes steps of: dividing the memory into memory banks accessible independently in read and write mode;...
7433992 Command controlling different operations in different chips  
In some embodiments, the invention includes a chip having a register to include an operation type signal. The chip also includes control circuitry to receive a first command and in response to the...
7433429 De-interleaver method and system  
In one embodiment, interleaved signals in a receiver are accessed by memory pointers and delivered to data stream locations without the need to transfer data to an intermediate physical buffer.
7424573 Information processing apparatus, method, and program for formatting multiple recording media integrated as one  
An information processing apparatus reads and writes information in a plurality of recording media is provided. The apparatus includes a formatting determination section which, in the case of...
7421564 Incrementing successive write operations to a plurality of memory devices  
A centralized memory allocation system utilizes write pointer drift correction. The memory stores data units. The memory controller receives a write request associated with a data unit and stores...
7417883 I/O data interconnect reuse as repeater  
Some embodiments may include a memory with a first memory device and data pins, and a second memory device coupled with some of the data pins of the first memory device, allowing the first memory...
7418540 Memory controller with command queue look-ahead  
In general, in one aspect, the disclosure describes accessing multiple memory access commands from a one of multiple memory access command queues associated with, respective, banks of a Random...
7415567 Memory hub bypass circuit and method  
A computer system and a method used to access data from a plurality of memory devices with a memory hub. The computer system includes a plurality of memory modules coupled to a memory hub...
7415565 Methods and systems for a storage system with a program-controlled switch for routing data  
A storage system that may include one or more memory devices, a memory interface device corresponding to one or more of the memory devices, which are organized in sections, a section controller,...
7409492 Storage system using flash memory modules logically grouped for wear-leveling and RAID  
A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory...
7406564 Distributed FIFO  
Circuits, methods, and apparatus for FIFO memories made up of multiple local memory arrays. These embodiments limit the number and length of interconnect lines that are necessary to join two or...
7404050 Method of operating a memory device, memory module, and a memory device comprising the memory module  
There is provided a method of operating a memory device comprising at least one memory module, a corresponding memory module and a memory device comprising the at least one memory module. It is...
7404047 Method and apparatus to improve multi-CPU system performance for accesses to memory  
Methods and apparatuses for improving processor performance in a multi-processor system by optimizing accesses to memory. Processors can track the state of a memory such that the memory can be...
7404057 System and method for enhancing read performance of a memory storage system including fully buffered dual in-line memory modules  
A system and method for enhanced read performance of a memory storage system is disclosed. The storage system includes a first memory controller. At least one first channel of a plurality of...
7404036 Rebalancing of striped disk data  
Provided are a method, system, and article of manufacture, where a plurality of extents are stored in a first set of storage units coupled to a controller. A determination is made that a second...
7404060 Apparatus, program, and method for managing usage of memory  
A memory management apparatus suitable for reducing amount of memory usage and simplifying programs is provided. When an area allocation request has been inputted, an unused area having a size...
7404048 Inter-cluster communication module using the memory access network  
An inter-cluster communication module using the memory access network is provided, including a plurality of clusters, a memory subsystem, a controller and a switch device. When some clusters issue...
7401177 Data storage device, data storage control apparatus, data storage control method, and data storage control program  
A data storage device includes a memory including a plurality of memory banks, a data storage processor that initially arranges data in the plurality of memory banks based on an access pattern...
7401169 Counter updating system using an update mechanism and different counter utilization mechanism  
Disclosed are, inter alia, methods, apparatus, data structures, computer-readable media, and mechanisms for maintaining counters, such as in, but not limited to a packet switching system, and...
7401176 Method and system for fast access to stack memory  
Fast access of a memory having a stack uses an address bit, a stack pointer, and fast access random access memory (“RAM”). When a first address mode is used in conjunction with the address bit and...
7401124 Apparatus and method to write information to two geographically separated virtual tape servers  
A method to write information to two geographically separated virtual tape servers, where the method provides a file to a virtual tape controller, writes that file to a first virtual tape server,...
7392339 Partial bank DRAM precharge  
A “partial PRECHARGE command” is used to precharge a fraction of the banks in a multi-bank DRAM. In a first implementation the command precharges one half of the banks. In a second implementation...
7389387 Distributed memory module cache writeback  
One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at...
7386596 High performance storage access environment  
The present invention provides improved techniques for managing storage resources, such as disk drives, I/O ports, and the like in a network based storage system according to a user position...
7386651 System, method, and apparatus for efficiently storing macroblocks  
Presented herein is a system for storing macroblocks for such that all vertically, horizontally, and diagonally adjacent macroblock are stored in different banks. When fetching a block from a...
7383416 Method for setting a second rank address from a first rank address in a memory module  
A method for setting an address of a rank in a memory module having a number of memory chips distributed along a byte lane includes setting the first memory chip of the byte lane to have a first...
7380048 System and method for managing data in memory for reducing power consumption  
A system or method to partition data in a memory based at least in part to a data type, and to refresh the memory based at least in part to the data type.
7373453 Method and apparatus of interleaving memory bank in multi-layer bus system  
A method and apparatus of interleaving memory banks in a multi-layer bus system. The apparatus includes a plurality of slave interface units receiving signals requesting a bus access and...
7370161 Bank arbiter system which grants access based on the count of access requests  
Provided are an arbiter capable of improving memory access efficiency in a multi-bank memory, a memory access arbitration system including the arbiter, and an arbitration method thereof, where the...
7366827 Method and apparatus for selectively transmitting command signal and address signal  
A method for transmitting a command signal and an address signal to a rank which is to be accessed includes receiving and buffering the command signal and the address signal, and transmitting the...
7366822 Semiconductor memory device capable of reading and writing data at the same time  
A semiconductor memory device includes a plurality of banks. A data path may be divided into a read data path and a write data path, therefore, parallel processing of write and read commands are...
7366821 High-speed memory system  
A memory system has a memory controller and a plurality of memories. The plurality of memories are connected via a switch to an end of a bus, which is connected to the memory controller, wherein...
7366820 Second-cache driving/controlling circuit, second cache, RAM, and second-cache driving/controlling method  
A circuit for driving and controlling a second cache that is incorporated in a processor and comprises a plurality of RAM. The circuit comprises a second-cache control unit 1A and a chip-enable...
7363419 Method and system for terminating write commands in a hub-based memory system  
A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub....
7363452 Pipelined burst memory access  
A memory device for multichannel continuous or fixed burst mode operation includes multiple burst address counter circuits and associated control logic to minimize latency which would otherwise...
7363458 Computer platform memory configuration on-board indicating method and system  
A computer platform memory configuration on-board indicating method and system is proposed, which is designed for use with a computer platform, such as a network server, for providing a memory...
7360040 Interleaver for iterative decoder  
Interleaver for iterative decoder. A memory management scheme allows for single plane/single port memory devices to be used by the interleaver. The design is adaptable to soft-in soft-out (SISO)...
7360038 Storage control system and method  
A storage control system comprises a first controller connected through a first access route to a first storage; a second controller connected through a second access route to a second storage...
7353357 Apparatus and method for pipelined memory operations  
A semiconductor memory device has a memory core that includes at least eight banks of dynamic random access storage cells and an internal data bus coupled to the memory core. The internal data bus...