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6530007 Method and apparatus for supporting heterogeneous memory in computer systems  
A memory controller capable of supporting heterogeneous memory configurations enables seamless communications between a bus and memory modules having different characteristics. Thus, owners of...
6526473 Memory module system for controlling data input and output by connecting selected memory modules to a data line  
A memory module system for connecting only selected memory modules to a data line to control data input and output is disclosed. The memory module system has a multiplicity of memory modules for...
6526471 Method and apparatus for a high-speed memory subsystem  
A high speed memory system is disclosed. The high speed memory system remembers the active n memory rows for n banks of memory. When a memory access request for a memory address that falls within...
6523060 Method and apparatus for the management of queue pointers by multiple processors in a digital communications network  
A method for managing a buffer queue that stores a data queue, wherein the data queue comprises a set of n data elements, n being at least zero. A head pointer is stored at a first location, which...
6523018 Neural chip architecture and neural networks incorporated therein  
The neural semiconductor chip first includes: a global register and control logic circuit block, a R/W memory block and a plurality of neurons fed by buses transporting data such as the input...
6513106 Mirror addressing in a DSP  
A method and system for implementing a mirror addressing scheme in conjunction with a symmetrical data table are disclosed. The method includes receiving a first address. In response to determining...
6510486 Clocking scheme for independently reading and writing multiple width words from a memory array  
The present invention provides a circuit for writing a particular sized data word from a common input to a number of individual memory cells in a memory array and reading a particular sized data...
6507886 Scheduler for avoiding bank conflicts in issuing concurrent requests to main memory  
A main memory scheduler includes a store, and stores therein requests for accessing main memory (such as a read request, a write request, or a refresh request). Normally, the main memory scheduler...
6507900 Semiconductor memory device including plural blocks with selecting and sensing or reading operations in different blocks carried out in parallel  
A memory device includes a plurality of blocks, each being capable of carrying out different types of operations, and a control unit for selecting one block after another from the plurality of...
6507884 Microcomputer with multiple memories for storing data  
A selection circuit causes either a memory 6 H or 6 L to enter an enabled state according to address data A 16 of address data A 0 -A 16 when a mode signal M is 1. The selection circuit...
6505282 Method and apparatus for determining memory types of a multi-type memory subsystem where memory of the different types are accessed using column control signals with different timing characteristics  
In a memory subsystem having a plurality of memory banks populated with up to a corresponding plurality of dynamic random access memory (DRAM) modules, the DRAM modules being of an extended data...
6502173 System for accessing memory and method therefore  
A specific embodiment is disclosed for a method and apparatus for processing data access requests from a requesting device, such as a graphics processor device. Data access commands are provided at...
6502162 Configuring vectors of logical storage units for data storage partitioning and sharing  
In a data storage subsystem providing data storage to host processors, a process of configuration defines a subset of the data storage that each host may access. A vector specification is a...
6502161 Memory system including a point-to-point linked memory subsystem  
A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device...
6499094 Management of memory heap space for data files accessible to programs operating in different addressing modes  
A method and apparatus for managing heap memory for an application program in a data processing system. The system supports a basic addressing mode and an extended addressing mode. Programs...
6493793 Content addressable memory device having selective cascade logic and method for selectively combining match information in a CAM device  
A content addressable memory (CAM) device having an array including a plurality of rows of CAM cells each coupled to a match line; match flag logic having inputs coupled to the match line, and...
6487140 Circuit for managing the transfer of data streams from a plurality of sources within a system  
A control circuit manages transferring of data within a system, such as an interleaved memory. The system includes a plurality of data sources for providing an output data stream synchronous with...
6483755 Memory modules with high speed latched sense amplifiers  
A fault-tolerant, high-speed wafer scale system comprises a plurality of functional modules, a parallel hierarchical bus which is fault-tolerant to defects in an interconnect network, and one or...
6480938 Efficient I-cache structure to support instructions crossing line boundaries  
A cache structure, organized in terms of cache lines, for use with variable length bundles of instructions (syllables), comprising: a first cache bank that is organized in columns and rows; a...
6477614 Method for implementing multiple memory buses on a memory module  
A computer system memory module includes a bi-directional repeater hub that in a first direction takes as an input a memory bus signal in a first port, regenerates the memory signals, and outputs...
6477630 Hierarchical row activation method for banking control in multi-bank DRAM  
A memory structure comprises a plurality of banks (each of the banks including a plurality of blocks) a plurality of timing critical address lines connected to all of the blocks in respective ones...
6470431 Interleaved data path and output management architecture for an interleaved memory and load pulser circuit for outputting the read data  
An interleaved memory having an interleaved data path includes an array of memory cells divided into a first bank of memory cells and a second bank of memory cells, first and second arrays of sense...
6467018 Method and apparatus for addressing individual banks of DRAMs on a memory card  
An improved memory card and its use in a computer system is provided. The computer system has a system bus which provides requests from a CPU to a memory controller, which then provides signals to...
6467015 High speed bus interface for non-volatile integrated circuit memory supporting continuous transfer  
A memory system with non-volatile integrated circuit memory devices including an interface for a high speed bus is described, supporting continuous writes at the bus speed, without the possibility...
6467013 Memory transceiver to couple an additional memory channel to an existing memory channel  
A memory repeater hub comprising a main memory channel interface circuit, an expansion control channel interface circuit, and an expansion memory channel interface circuit. The main memory channel...
6463500 Apparatus and method to access computer memory by processing object data as sub-object and shape parameter  
A method is provided for utilizing a memory system which allows for the fast and efficient writing and reading of objects to and from diverse memory chips. A computer system and memory system...
6457094 Memory array architecture supporting block write operation  
A memory array architecture that supports block write operation and has many advantages over conventional memory array architectures. A memory array is partitioned into a number of (N) segments....
6457110 Method of accessing syncronous dynamic random access memory in scanner  
A method of reading data from a synchronous dynamic random access memory inside a scanner. The synchronous dynamic random access memory has a plurality of memory banks. A batch of random access...
6453380 Address mapping for configurable memory system  
In a system in which data are stored in an interleaved fashion in a memory consisting of a plurality of memory banks, a method and means are provided for mapping a given address into a memory bank...
6449681 Memory unit and buffer access control circuit for updating an address when consecutively accessing upper and lower buffers  
A buffer access control circuit to access a buffer which is divided into an upper buffer and a lower buffer which are assigned the same address and a memory unit including the buffer access control...
6446163 Memory card with signal processing element  
A memory card having a memory bus controller is provided which card has a signal processing element preferably a digital signal processor (DSP) thereon, which card is used in a computer system as...
6446157 Cache bank conflict avoidance and cache collision avoidance  
The inventive mechanism determines whether memory source and destination addresses map to the same or nearly the same cache address. If they map to different addresses, then loads and stores are...
6445825 Apparatus and method of generating compressed data  
Compression and encoding sections ( 311 ( 1 ), 311 ( 2 ) and 311 ( 3 ) compress and encode input signals VS, AS and SS separately to generate compressed data. A SCSI interface ( 32 ) outputs...
6446184 Address re-mapping for memory module using presence detect data  
A memory module comprising: a plurality of memory devices associated with the module; each of the memory devices being configured in M banks; and a logic circuit for configuring the memory module...
6446158 Memory system using FET switches to select memory banks  
A computer memory system provides a double data rate (DDR) memory output while requiring memory chips with only half the frequency limit of the prior art DDR memory chips. The system contains a...
6446183 Systems and methods for persistent and robust memory management  
A method for managing persistent storage in a memory storage system including a main memory and at least one disk memory device, in accordance with the invention, includes maintaining headers in...
6442667 Selectively powering X Y organized memory banks  
This invention is memory system including plural memory banks logically disposed into an array of X rows and Y columns. A first decoder selectively powers one of the Y columns corresponding to a...
6434679 Architecture for vital data management in a multi-module machine and process for implementing an architecture of this type  
The invention relates to an architecture for management of vital data in a multi-module digital data processing machine ( 1 ) and the process for its implementation. Each module (M 1 through M n )...
6430672 Method for performing address mapping using two lookup tables  
A method for performing address mapping for a memory within a computer system is disclosed. The memory is organized in multiple of memory banks, and each memory bank is identified by a respective...
6430647 Data processing system for use in conjunction with a font card or the like  
A data processing system provided with a CPU for reading at units of 32 bits per read cycle, a font card that requires read accesses of either 16 or 8 bits per cycle by accessing a specific address...
6430648 Arranging address space to access multiple memory banks  
An improved and much simplified method to address memory space having multiple memory banks in memory such as those in computer systems. The method provides absolute addressing and treats the...
6425044 Apparatus for providing fast memory decode using a bank conflict table  
One embodiment of the present invention provides a system that rapidly determines whether a bank conflict exists during a memory access operation. The system includes an input that receives an...
6425045 Reducing memory latency by not performing bank conflict checks on idle banks  
A computer system includes a memory device including banks, and a memory interface coupled to the memory device. The memory interface is adapted to store requests that are associated with the...
6425043 Method for providing fast memory decode using a bank conflict table  
One embodiment of the present invention provides a method for rapidly determining whether a bank conflict exists during a memory access. The method operates by receiving an address as part of a...
6415363 Memory statistics counter and method for counting the number of accesses to a portion of memory  
A memory statistic counter and method for counting the number of accesses (writes or reads) by a microprocessor ( 10 ) to at least a portion of a memory comprising a decoding logic unit ( 16 ) for...
6412039 Cross-bank, cross-page data accessing and controlling system  
A cross memory bank, cross memory page data accessing and controlling unit that provides more efficient transfer of data between a CPU and a memory cluster is described. The data accessing and...
6405286 Method and apparatus for determining interleaving schemes in a computer system that supports multiple interleaving schemes  
A method and apparatus determines interleaving schemes in a computer system that supports multiple interleaving schemes. In one embodiment, a memory interleaving scheme lookup table is used to...
6401180 Bank history table for improved pre-charge scheduling of random access memory banks  
A bank history table and precharge decision logic allows a memory controller to dynamically choose either to precharge a memory bank immediately after an access or to delay precharge based on the...
6401160 Method and apparatus to permit adjustable code/data boundary in a nonvolatile memory  
A method of moving a boundary in a nonvolatile memory is disclosed. The method comprises identifying a boundary location in the nonvolatile memory. The boundary location comprises a position...
6401162 Generalized fourier transform processing system  
Improved Fourier transform processing systems for a data transmission system are disclosed. The improved Fourier transform processing systems efficiently performs Fourier transform signal...
Matches 501 - 550 out of 1061 < 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 >