Match Document Document Title
7577760 Memory systems, modules, controllers and methods using dedicated data and control busses  
A memory system includes a plurality of memory devices arranged in sets on at least one memory module, each set including at least one memory device. In some embodiments, the system further...
7574573 Reactive placement controller for interfacing with banked memory storage  
An invention is provided for a reactive placement controller for interfacing with a banked memory storage. The reactive placement controller includes a read/write module, which is coupled to a...
7571274 Method and system for virtual enclosure management  
A process and system for virtually managing enclosures. A process determines whether a system includes an enclosure processor, a virtual enclosure processor, or both an enclosure processor and a...
7564727 Apparatus and method for configurable power management  
A method and apparatus to facilitate low-power consumption through a configurable suspend mode of operation of a PLD, the PLD comprising an application logic block coupled to receive configuration...
7565343 Search apparatus and search management method for fixed-length data  
Fixed-length data (560) contained in a database (560) are segmented into a number of pieces of data that are searchable at a time and searching is performed at high speed. As means for it, a...
7562184 DRAM controller for graphics processing operable to enable/disable burst transfer  
An interface unit 20 assigns different SDRAMs 1 and 2 to adjacent drawing blocks in a frame-buffer area. In processing that extends across the adjacent drawing blocks, active commands, for...
7562178 Memory hub and method for memory sequencing  
A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics—for example, page hit rate,...
7562202 Systems, methods, computer readable medium and apparatus for memory management using NVRAM  
A system and method is disclosed for improving data integrity and the efficiency of data storage in separate memories of a computing device. In particular, the present invention introduces a...
7558933 Synchronous dynamic random access memory interface and method  
A memory interface allows access SDRAM by receiving a column address for a data read or write of a burst of data units. Each data unit in the burst has an expected bit size. The interface...
7558934 Data storage unit, data storage controlling apparatus and method, and data storage controlling program  
A data storage unit is provided in which all data are stored into a memory including a plurality of memory banks and a plurality of desired data is read simultaneously, without any load to the...
7558908 Structure of sequencers that perform initial and periodic calibrations in a memory system  
A structure of sequencers, a method, and a computer program are provided for performing initial and periodic calibrations in an XDR™ memory system. A memory controller that performs these...
7549013 Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices  
In one embodiment of the present invention, a memory storage system for storing information organized in sectors within a nonvolatile memory bank is disclosed. The memory bank is defined by sector...
7546451 Continuously providing instructions to a programmable device  
A system and method for enabling a programmable device to execute instructions without interruption. An instruction space for storing instructions from a host application is bifurcated to define a...
7545664 Memory system having self timed daisy chained memory chips  
A memory system having a memory controller and a memory. The memory comprises one or more daisy chains of self timed memory chips. An address/command word is chained through a daisy chain of...
7546386 Method for virtual resource initialization on a physical adapter that supports virtual resources  
A method for directly sharing a network stack offload I/O adapter that directly supports resource virtualization and does not require a LPAR manager or other intermediary to be invoked on every...
7546424 Embedded processor with dual-port SRAM for programmable logic  
Methods and apparatus for programmable logic devices including embedded processors having a dual-port SRAMs. A programmable logic integrated circuit includes a programmable logic portion having a...
7543106 Apparatus and method for controlling refresh of semiconductor memory device according to positional information of memory chips  
A memory controller controlling a plurality of semiconductor memory devices includes a refresh control circuit controlling refresh operations of the semiconductor memory devices according to...
7543102 System and method for performing multi-rank command scheduling in DDR SDRAM memory systems  
A DRAM command scheduling algorithm is presented that is designed to alleviate various constraints imposed upon high performance, high datarate, short channel DDRx SDRAM memory systems. The...
7539842 Computer memory system for selecting memory buses according to physical memory organization information stored in virtual address translation tables  
Systems and methods for program directed memory access patterns including a memory system with a memory, a memory controller and a virtual memory management system. The memory includes a plurality...
7539811 Scaleable memory systems using third dimension memory  
A non-volatile scalable memory circuit is described, including a bus formed on a substrate that includes active circuitry, metallization layers, and a plurality of high density third dimension...
7536519 Memory access control apparatus and method for accomodating effects of signal delays caused by load  
A memory controller determines a load level based on the number of connected memory devices informed by a switch or the like. If it is determined that the load level is high, the memory controller...
7536499 Memory access control device and processing system having same  
A memory access control device enabling freer access from a plurality of ports to a plurality of memories and a processing system having the same are provided. From among addresses generated at a...
7533213 Memory hub and method for memory system performance monitoring  
A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics—for example, page hit rate,...
7533212 System memory board subsystem using DRAM with integrated high speed point to point links  
A memory system comprising memory modules including memory chips including integrated switching circuits. A memory controller coupled to the memory modules is configured to initiate memory...
7526596 ***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***
Methods and systems for an identifier-based memory section
 
A storage system that may include one or more memory devices, a memory interface device corresponding to one or more of the memory devices, which are organized in sections, and a section...
7526597 Buffered memory having a control bus and dedicated data lines  
A memory system architecture/interconnect topology includes a configurable width buffered module having a configurable width buffer device. The configurable width buffer device is coupled to at...
7523230 Device and method for maximizing performance on a memory interface with a variable number of channels  
The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of...
7523248 System having a controller device, a buffer device and a plurality of memory devices  
A system comprises a controller device, an integrated circuit buffer device and a first and second memory device. A first plurality of signal lines is coupled to the controller device. A second...
7519762 Method and apparatus for selective DRAM precharge  
Apparatus and method for using a precharge command in which a plurality of address lines are individually used to specify which banks of memory cells within a memory device have an open row that...
7519696 Method and apparatus for dynamically modifying a computer system configuration  
One embodiment is directed to a method and apparatus for modifying a configuration of a computer system including a host computer and at least one computer system resource accessible to at least...
7516264 Programmable bank/timer address folding in memory devices  
A set of N copies of bank control logic are provided for tracking the banks within the memory modules (DRAMS). When the total number of banks within the memory module(s) is greater than N, the...
7516282 Control device and control method for memory  
A control device for a memory is provided. The control device includes a micro-control unit (MCU), a command queue, a command sequencer, and a table. The control device is coupled to the memory...
7512847 Method for estimating and reporting the life expectancy of flash-disk memory  
A method for managing a memory device, a memory device so managed and a system that includes such a memory device. A value of a longevity parameter of the device is monitored after a data...
7508706 Nonvolatile semiconductor memory device provided with data register for temporarily holding data in memory array  
A precharge signal generation circuit outputs a precharge signal including a pulse every access cycle with respect to a data register in a first mode, and generates a precharge signal by masking...
7509302 Device, method and program for providing a high-performance storage access environment while issuing a volume access request including an address of a volume to access  
The present invention provides a high-performance storage access environment to a user who moves around a wide area, while increasing the fault resistance of the system. A plurality of network...
7505356 Multi-column addressing mode memory system including an integrated circuit memory device  
A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit...
7506130 Mirrored computer memory on split bus  
A fully mirrored memory system includes at least one split memory bus, with each portion of the split memory bus having active memory and mirror memory. Each portion of the memory bus transfers a...
7499954 Consistent reintegration of a failed primary instance  
A method and system are provided for providing a consistent reintegration of a failed primary instance as a new secondary instance with implementation of truncation of log records. Upon failure of...
7496777 Power throttling in a memory system  
A memory system is disclosed. The memory system includes a memory controller coupled to one or more memory modules, at least one of the memory modules including a buffer. The memory controller is...
7493441 Mass storage controller with apparatus and method for extending battery backup time by selectively providing battery power to volatile memory banks not storing critical data  
A battery-backed write-caching mass storage controller is disclosed. The controller includes a plurality of volatile memory banks for caching write data prior to being written to disk drives....
7493457 States encoding in multi-bit flash cells for optimizing error rate  
To store N bits of M≧2 logical pages, the bits are interleaved and the interleaved bits are programmed to ┌N/M┐ memory cells, M bits per cell. Preferably, the interleaving puts the same number of...
7493469 Performance evaluation apparatus, performance evaluation method, program and computer readable recording medium  
From an application program described in the form of a flow graph, input and output arcs are extracted. Packet rates on the input and output arcs are extracted, and it is determined whether the...
7490217 Design structure for selecting memory busses according to physical memory organization information stored in virtual address translation tables  
Design structures for program directed memory access patterns. A design structure is embodied in a machine readable storage medium used in a design process, the design structure including a...
7489571 Semiconductor device for switching a defective memory cell bit of data to replacement data on the output data line  
A semiconductor device is provided for outputting data read from a read only storage device. The semiconductor device includes a read only storage device including memory cells, an address signal...
7490190 Method and system for local memory addressing in single instruction, multiple data computer system  
A single instruction, multiple data (“SIMD”) computer system includes a central control unit coupled to 256 processing elements (“PEs”) and to 32 static random access memory (“SRAM”) devices. Each...
7487301 Method and system for accelerated access to a memory  
Method of transferring data between a memory comprising several banks and a data processing circuit, the method comprising the steps of: producing access requests (46, 47) defining each time a...
7487318 Managing write-to-read turnarounds in an early read after write memory system  
Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read...
7480781 Apparatus and method to merge and align data from distributed memory controllers  
We describe a system and method to merge and align data from distributed memory controllers. A memory system includes a command bus to transmit a predetermined memory access command, and a memory...
7480759 System, method and storage medium for providing data caching and data compression in a memory subsystem  
A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory...
7478213 Off-chip micro control and interface in a multichip integrated memory system  
A communication interface, coupling a controller device to one or more memory devices, provides a high-voltage reset interface. The high-voltage reset interface provides a high-voltage signal to...