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7606807 |
Method and apparatus to utilize free cache in a storage system
A system is provided to improve performance of a storage system. The system comprises a multi-tier buffer cache. The buffer cache may include a global cache to store resources for servicing...
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7603510 |
Semiconductor device and storage cell having multiple latch circuits
A semiconductor storage device including a first latch circuit for latching stored data and a storage cell part including a plurality of second latch circuits that operate with inverted logic from...
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7596738 |
Method and apparatus for classifying memory errors
One embodiment of the present invention provides a system that determines the cause of a correctable memory error. First, the system detects a correctable error during an access to a memory...
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7596669 |
Apparatus and method for managing memory in a network switch
The present invention is related to a method and apparatus for managing memory in a network switch, wherein the memory includes the steps of providing a memory, wherein the memory includes a...
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7594087 |
System and method for writing data to and erasing data from non-volatile memory
A method and system for accessing a non-volatile memory is disclosed. The method includes writing a first stream of data to a first block of a first region of a non-volatile memory and detecting a...
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7590792 |
Cache memory analyzing method
It is done to read information containing an address of a memory at which a cache miss is generated, from a cache memory. The numbers of cache misses generated at each cache miss generated address...
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7584206 |
File recording method and file recording apparatus
A method and apparatus that, when generating a multimedia file in which encoded data management information is placed at the head of the file, estimates the size needed for the management...
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7581083 |
Operation processing device, system and method having register-to-register addressing
As shown in FIG. 1, an operation-processing device of the present invention comprises a register array ( 11 ) having plural registers for holding an arbitrary value based on a write address Aw...
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7555591 |
Method and system of memory management
The disclosure is directed to a computational system including a processor, cache memory accessible to the processor, and a memory management unit accessible to the processor. The processor is...
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7536692 |
Thread-based engine cache partitioning
In general, in one aspect, the disclosure describes a processor that includes an instruction store to store instructions of at least a portion of at least one program and multiple engines coupled...
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7526610 |
Sectored cache memory
A memory cache comprising, a data sector having a sector ID, wherein the data sector stores a data entry, a primary directory having a primary directory entry, wherein a position of the primary...
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7519470 |
Location-based caching for mobile devices
A location-based caching system provides the ability for a mobile communication device to dynamically provide content related to a user's location. Content may comprise a series of map segments...
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7512837 |
System and method for the recovery of lost cache capacity due to defective cores in a multi-core chip
A method for recovering lost cache capacity in a multi core chip having at least one defective core including identifying the cores contained in the chip that are viable cores and identifying at...
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7505168 |
Distributed client side printing methods and systems
Various distributed client side printing methods and systems are described. In at least some embodiments, printer control and the job handling functions are bifurcated or separated by allowing...
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7490200 |
L2 cache controller with slice directory and unified cache structure
A cache memory logically partitions a cache array having a single access/command port into at least two slices, and uses a first cache directory to access the first cache array slice while using a...
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7480759 |
System, method and storage medium for providing data caching and data compression in a memory subsystem
A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory...
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7478202 |
Using the message fabric to maintain cache coherency of local caches of global memory
Described is a technique for maintaining local cache coherency between endpoints using the connecting message fabric. Processors in a data storage system communicate using the message fabric. Each...
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7475219 |
Serially indexing a cache memory
In one embodiment, the present invention includes a method of accessing a cache memory to determine whether requested data is present. In this embodiment, the method may include indexing a cache...
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7475093 |
Memory cache management in XML/relational data mapping
Caching architecture that facilitates translation between schema data and relational structures. A schema translation component consumes schema data (e.g., XML schema data) having a schema...
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7472218 |
Assisted trace facility to improve CPU cache performance
A system and method for recording trace data while conserving cache resources includes generating trace data and creating a cache line containing the trace data. The cache line is assigned a tag...
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7469318 |
System bus structure for large L2 cache array topology with different latency domains
A cache memory which loads two memory values into two cache lines by receiving separate portions of a first requested memory value from a first data bus over a first time span of successive clock...
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7467377 |
Methods and apparatus for compiler managed first cache bypassing
Methods and apparatus to manage bypassing of a first cache are disclosed. In one such method, a load instruction having an expected latency greater than or equal to a predetermined threshold is...
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7464240 |
Hybrid solid state disk drive with controller
A solid-state disk drive includes a first portion of solid-state memory of a volatile nature, a second portion of solid-state memory of a non-volatile nature, a controller for managing the...
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7464181 |
Method for caching lookups based upon TCP traffic flow characteristics
The classification system of a network device includes a cache in which a mapping between predefined characteristics of TCP/IP packets and associated actions are stored in response to the first...
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7461229 |
Software program for managing and protecting data written to a hybrid solid-state disk drive
A machine-readable medium is provided having stored thereon a set of instructions that cause a controller of solid-state disk having a first portion of solid-state memory of a volatile nature and a...
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7451271 |
Physically-tagged cache with virtually-tagged fill buffers
A virtually indexed, physically-tagged cache is combined with one or more virtually-tagged fill-buffers.
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7451261 |
Data storage device and control method with buffer control thereof
Embodiments of the invention improve the cache hit ratio of read data. A hard disk drive (HDD) according to an embodiment of the present invention determines whether the read buffer should be used...
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7451248 |
Method and apparatus for invalidating cache lines during direct memory access (DMA) write operations
A method and apparatus for invalidating cache lines during direct memory access (DMA) write operations are disclosed. Initially, a multi-cache line DMA request is issued by a peripheral device. The...
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7444457 |
Retrieving data blocks with reduced linear addresses
Systems and methods of processing addresses provide for receiving a full linear address of an instruction and reducing a size of the full linear address to obtain a reduced linear address. A data...
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7441074 |
Methods and apparatus for distributing entries among lookup units and selectively enabling less than all of the lookup units when performing a lookup operation
Methods and apparatus are disclosed for distributing entries among lookup units and selectively enabling less than all of the lookup units when performing a lookup operation. Each of the lookup...
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7424587 |
Methods for managing data writes and reads to a hybrid solid-state disk drive
A method for writing data to a solid-state disk having a first portion of solid-state memory of a volatile nature and a second portion of solid-state memory of a non-volatile nature, and a...
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7418583 |
Data dependency detection using history table of entry number hashed from memory address
A detector detects at least one kind of dependence in address between instructions executed by at least a processor, the detector being adopted to detect a possibility of presence of the at least...
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7412569 |
System and method to track changes in memory
Briefly, a system and a method to efficiently track changes in memory or storage areas, for example, in cache memories of computers and electronic systems. A method in accordance with an exemplary...
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7412568 |
Method for thread caching
Methods, apparatus, and systems are provided for caching. A caching process is automatically modified in response to update eligibility and an interference relation for a plurality of threads. Data...
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7406569 |
Instruction cache way prediction for jump targets
Typical cache architecture provides a single cache way prediction memory for use in predicting a cache way for both sequential and non-sequential instructions contained within a program stream....
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7406566 |
Ring interconnect with multiple coherence networks
A cache architecture to increase communication throughput and reduce stalls due to coherence protocol dependencies, while reducing power within an integrated circuit. More particularly, embodiments...
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7404044 |
System and method for data transfer between multiple processors
A system and method are provided for increasing the number of processors on a single integrated circuit to a number that is larger than would typically be possible to coordinate on a single bus. In...
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7401184 |
Matching memory transactions to cache line boundaries
In general, in one aspect, the disclosure describes a method that includes generating multiple cache line accesses to multiple respective cache lines of a cache as required to satisfy an access to...
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7395380 |
Selective snooping by snoop masters to locate updated data
A method and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has cache memory, and wherein some, but less...
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7389385 |
Methods and apparatus to dynamically insert prefetch instructions based on compiler and garbage collector analysis
Methods and apparatus to insert prefetch instructions based on garbage collector analysis and compiler analysis are disclosed. In an example method, one or more batches of samples associated with...
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7386596 |
High performance storage access environment
The present invention provides improved techniques for managing storage resources, such as disk drives, I/O ports, and the like in a network based storage system according to a user position within...
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7380098 |
Method and system for caching attribute data for matching attributes with physical addresses
A method for caching attribute data for matching attributes with physical addresses. The method includes storing a plurality of attribute entries in a memory, wherein the memory is configured to...
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7380047 |
Apparatus and method for filtering unused sub-blocks in cache memories
A memory system and method includes a cache having a filtered portion and an unfiltered portion. The unfiltered portion is divided into block sized components, and the filtered portion is divided...
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7373466 |
Method and apparatus for filtering memory write snoop activity in a distributed shared memory computer
A method and apparatus for filtering memory probe activity for writes in a distributed shared memory computer. In one embodiment, the method may include assigning an uncached directory state to a...
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7366820 |
Second-cache driving/controlling circuit, second cache, RAM, and second-cache driving/controlling method
A circuit for driving and controlling a second cache that is incorporated in a processor and comprises a plurality of RAM. The circuit comprises a second-cache control unit 1 A and a chip-enable...
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7366819 |
Fast unaligned cache access system and method
A cache unit multiple memory towers, which can be independently addressed. Cache lines are divided among multiple towers. Furthermore, physical lines of the memory towers are shared by multiple...
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7366801 |
Method for buffering work requests
Disclosed is a technique for buffering work requests. It is determined that a work request is about to be placed into an in-memory structure. When the in-memory structure is not capable of storing...
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7355601 |
System and method for transfer of data between processors using a locked set, head and tail pointers
A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task...
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7353326 |
Flash memory device supporting cache read operation
A flash memory device comprises a non-volatile memory core operatively connected to first and second buffer memories through a page buffer. The device further comprises a first register adapted to...
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7353221 |
Method for the automatic retrieval of engineering data of systems
The invention relates to a method for the automatic retrieval of engineering data from installations. The engineering and runtime objects are described by a uniform object model. This allows the...
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