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9021401 Methods and systems involving browser nodes  
A method comprises creating a first node, determining whether an indicator associated with a head node is present, and designating the first node as a head node, defining and associating a head...
8949572 Effective address cache memory, processor and effective address caching method  
An effective address cache memory includes a TLB effective page memory configured to retain entry data including an effective page tag of predetermined high-order bits of an effective address of a...
8924648 Method and system for caching attribute data for matching attributes with physical addresses  
A method for caching attribute data for matching attributes with physical addresses. The method includes storing a plurality of attribute entries in a memory, wherein the memory is configured to...
8924359 Cooperative tiering  
Various systems and methods for cooperative tiering between an application and a storage device. One method can include receiving information from the application where the information identifies...
8898424 Memory address translation  
The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array...
8862828 Sub-numa clustering  
Method and apparatus to efficiently store and cache data. Cores of a processor and cache slices co-located with the cores may be grouped into a cluster. A memory space may be partitioned into...
8856454 Anticipatory response pre-caching  
Interaction between a client and a service in which the service responds to requests from the client. In addition to responding to specific client requests, the service also anticipates or...
8856474 Nonvolatile memory unit with secure erasing function  
An apparatus includes a nonvolatile memory, an interface that at least receives an erase command of the nonvolatile memory, a first controller that controls the nonvolatile memory to execute data...
8850118 Circuit and method for dynamically changing reference value for address counter based on cache determination  
A memory access determination circuit includes a counter that switches between a first reference value and a second reference value in accordance with a control signal to generate a count value...
8843690 Memory conflicts learning capability  
An apparatus having a memory and circuit is disclosed. The memory may (i) assert a first signal in response to detecting a conflict between at least two addresses requesting access to a block at a...
8838936 System and method for efficient flash translation layer  
A method of maintaining and updating a logical-to-physical (LtoP) table in a storage device including a processor, a volatile memory, and a non-volatile memory, the storage device being in...
8831229 Key transport method, memory controller and memory storage apparatus  
A key transport method for transporting a key from a buffer memory to an encryption/decryption unit is provided. The method includes logically dividing bits of the key into key segments, wherein...
8819392 Providing metadata in a translation lookaside buffer (TLB)  
In one embodiment, the present invention includes a translation lookaside buffer (TLB) to store entries each having a translation portion to store a virtual address (VA)-to-physical address (PA)...
8812789 Systems and methods for cache line replacement  
A computer readable storage medium includes instructions that, when executed by a processor, cause the processor to receive an index value included in a cache invalidate by index instruction, an...
8806142 Anticipatory response pre-caching  
Interaction between a client and a service in which the service responds to requests from the client. In addition to responding to specific client requests, the service also anticipates or...
8806101 Metaphysical address space for holding lossy metadata in hardware  
A method and apparatus for metaphysical address space for holding lossy metadata is herein described. An explicit or implicit metadata access operation referencing data address of a data item is...
8806141 List based prefetch  
A list prefetch engine improves a performance of a parallel computing system. The list prefetch engine receives a current cache miss address. The list prefetch engine evaluates whether the current...
8806102 Cache system  
A cache system includes a primary cache memory configured to input and output data between a computation unit, the primary cache memory includes multi-port memory units each including a storing...
8782667 Weather adaptive environmentally hardened appliances  
Embodiments of the present invention provide a method, system and computer program product for weather adaptive environmentally hardened appliances. In an embodiment of the invention, a method for...
8756400 ***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***
Memory address translation
 
The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array...
8751751 Method and apparatus for minimizing cache conflict misses  
A method for minimizing cache conflict misses is disclosed. A translation table capable of facilitating the translation of a virtual address to a real address during a cache access is provided....
8745307 Multiple page size segment encoding  
An approach identifies an amount of high order bits used to store a memory address in a memory address field that is included in a memory. This approach calculates at least one minimum number of...
8719502 Adaptive self-repairing cache  
A method for operating a cache that includes both robust cells and standard cells may include receiving a data to be written to the cache, determining whether a type of the data is unmodified data...
8694924 Mobile terminal having function of managing file and folder  
A mobile terminal having a function of managing files and folders is disclosed. In one embodiment, the mobile terminal displays folder items representing one or more memory elements installed in...
8688890 Bit ordering for communicating an address on a serial fabric  
A method for handling a request of storage on a serial fabric comprising formatting an address for communication on a serial fabric into a plurality of fields including a field comprising at least...
8688913 Management of partial data segments in dual cache systems  
For movement of partial data segments within a computing storage environment having lower and higher levels of cache by a processor, a whole data segment containing one of the partial data...
8688962 Gather cache architecture  
Apparatuses and methods to perform gather instructions are presented. In one embodiment, an apparatus comprises a gather logic module which includes a gather logic unit to identify locality of...
8681169 Sparse texture systems and methods  
Systems and methods for texture processing are presented. In one embodiment a texture method includes creating a sparse texture residency translation map; performing a probe process utilizing the...
8677049 Region prefetcher and methods thereof  
A prefetch device and method are disclosed that determines from which addresses to speculatively fetch data based on information collected regarding previous cache-miss addresses. A historical...
8677050 System, method and computer program product for extending a cache using processor registers  
According to one aspect of the present disclosure, a method and technique for using processor registers for extending a cache structure is disclosed. The method includes identifying a register of...
8661179 Cache memory architecture having reduced tag memory size and method of operation thereof  
A cache memory architecture, a method of operating a cache memory and a memory controller. In one embodiment, the cache memory architecture includes: (1) a segment memory configured to contain at...
8655842 Push pull caching for social network information  
Embodiments are directed towards modifying a distribution of writers as either a push writer or a pull writer based on a cost model that decides for a given content reader whether it is more...
8627039 Effective memory clustering to minimize page fault and optimize memory utilization  
An embodiment of the invention provides a method for organizing data addresses within a virtual address space to reduce the number of data fetches to a cloud computing environment. More...
8619790 Adaptive cache for caching context and for adapting to collisions in a session lookup table  
Certain embodiments of the invention may be found in a method and system for an adaptive cache for caching context and for adapting to collisions in session lookup table. A network processor chip...
8599707 Power based content modification, transmission, and caching  
Methods and apparatus for operating a mobile device based upon a power capability of the mobile device are disclosed. In one embodiment, the mobile device includes a network selection component...
8566564 Method and system for caching attribute data for matching attributes with physical addresses  
A method for caching attribute data for matching attributes with physical addresses. The method includes storing a plurality of attribute entries in a memory, wherein the memory is configured to...
8560795 Memory arrangement for multi-processor systems including a memory queue  
A hardware memory architecture or arrangement suited for multi-processor systems or arrays is disclosed. In one aspect, the memory arrangement includes at least one memory queue between a...
8549208 Cache memory having enhanced performance and security features  
A cache memory having enhanced performance and security feature is provided. The cache memory includes a data array storing a plurality of data elements, a tag array storing a plurality of tags...
8539185 Systolic networks for a spiral cache  
Systolic networks within a tiled storage array provide for movement of requested values to a front-most tile, while making space for the requested values at the front-most tile by moving other...
8521944 Performing memory accesses using memory context information  
In one embodiment, a processor includes an address generation unit having a memory context logic to determine whether a memory context identifier associated with an address of a memory access...
8495435 Dynamic physical memory replacement through address swapping  
An apparatus, system, method, and machine-readable medium are disclosed. In one embodiment the apparatus includes an address swap cache. The apparatus also includes memory segment swap logic that...
8489815 Managing cache data and metadata  
Embodiments of the invention provide techniques for managing cache metadata providing a mapping between addresses on a storage medium (e.g., disk storage) and corresponding addresses on a cache...
8489817 Apparatus, system, and method for caching data  
An apparatus, system, and method are disclosed for caching data. A storage request module detects an input/output (“I/O”) request for a storage device cached by solid-state storage media of a...
8468531 Method and apparatus for efficient inter-thread synchronization for helper threads  
A monitor bit per hardware thread in a memory location may be allocated, in a multiprocessing computer system having a plurality of hardware threads, the plurality of hardware threads sharing the...
8464000 Systems and methods for cache line replacements  
A system for determining a cache line to replace is described. In one embodiment, the system includes a cache comprising a plurality of cache lines. The system further includes an identifier...
8438003 Methods for improved simulation of integrated circuit designs  
A method of improved simulator processing is provided. The method according to the current invention includes grouping frequently accessed data into one set id to improve memory hierarchy...
8417914 Memory address translation  
The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array...
8407392 Fast unaligned cache access system and method  
A cache unit multiple memory towers, which can be independently addressed. Cache lines are divided among multiple towers. Furthermore, physical lines of the memory towers are shared by multiple...
8402198 Mapping engine for a storage device  
A hardware search structure quickly determines the status of cache lines associated with a large disk array and at the same time reduces the amount of memory space needed for tracking the status....
8370604 Method and system for caching attribute data for matching attributes with physical addresses  
A method for caching attribute data for matching attributes with physical addresses. The method includes storing a plurality of attribute entries in a memory, wherein the memory is configured to...