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6430684 |
Processor circuits, systems, and methods with efficient granularity shift and/or merge instruction(s)
A method of operating a processor (30). The method comprises a first step of fetching an instruction (20). The instruction includes an instruction opcode, a first data operand bit group...
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6430672 |
Method for performing address mapping using two lookup tables
A method for performing address mapping for a memory within a computer system is disclosed. The memory is organized in multiple of memory banks, and each memory bank is identified by a respective...
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6430671 |
Address generation utilizing an adder, a non-sequential counter and a latch
An integrated circuit, e.g. an AC '97 conforming audio codec, includes a digital filter and gain module including multiple channels of gain control and multiple channels of digital filtering. A...
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6427200 |
Multiple changeable addressing mapping circuit
A multiple changeable addressing mapping circuit is disclosed for converting an input logic address of a field array in a data array into an output physical address. The circuit has multiple...
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6425065 |
Tag RAM with selection module for a variable width address field
A tag RAM is coupled to an address bus that is adapted to carry a variable width address field. The tag RAM includes a memory section coupled to the address bus and a comparator coupled to the...
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6425067 |
Systems and methods for implementing pointer management
A system and method of compressing memory for efficiently searching the memory. Values are assigned to initial memory locations and these values are logically combined to form a first group of...
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6421825 |
Register control apparatus and method thereof for allocating memory based on a count value
In a register controlling apparatus, whenever a routine is run, a register logicalal address, and the values of a local register pointer and a local register counter are selectively added, and...
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6411552 |
Data processing system, block erasing type memory device and memory medium storing program for controlling memory device
A data processing system is provided with a flash memory including a plurality of blocks and capable of erasing stored data collectively in units of block and a memory control unit for accessing...
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6408374 |
Hashing method and apparatus
A hashing method and apparatus uses a hash function that can be modified in real time by a hash control code. The hash function involves the combining together of multiple bit-shifted versions of a...
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6405298 |
Linear address generator and method for generating a linear address using parallel computations and a single cycle algorithm
A high-speed linear address generator (LAGEN) and method for generating a linear address are disclosed, which generator is operable to generate a linear address very quickly. In a preferred...
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6401185 |
Method and apparatus for accessing paged objects using a fast division technique
A fast division technique is provided to calculate the address of a slot in a paged object, when the slot is located on a different page than the beginning of the object. The fast division...
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6400293 |
Data compression system and method
A system for encoding data is provided. The system includes a number parser that breaks down a field that has many digits into a set of data strings that each has a fixed number of digits. A...
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6397318 |
Address generator for a circular buffer
This invention describes an apparatus and method for the fast and efficient generation of addresses for a circular buffer involving only addition. The invention uses as input the present address,...
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6397324 |
Accessing tables in memory banks using load and store address generators sharing store read port of compute register file separated from address register file
A very long instruction word (VLIW) processor typically requires a large number of register file ports due to the parallel execution of the sub-instructions comprising the VLIW. By splitting a...
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6397326 |
Method and circuit for preloading prediction circuits in microprocessors
A method and circuit is provided for preloading a branch prediction unit within a microprocessor. In one embodiment of the method, a branch history storage device such as branch history shift...
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6397291 |
Method and apparatus for retrieving data from a data storage device
A data retrieval system receives a data address identifying data to be retrieved. A portion of the received data address is communicated to a data storage device during a first clock cycle. The...
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6393544 |
Method and apparatus for calculating a page table index from a virtual address
A method and apparatus calculate a page table index from a virtual address. Employs a combined hash algorithm that supports two different hash page table configurations. A “short format” page tab...
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6388586 |
Method for reversing the bits of a computer data structure
The bits comprising a computer data structure are reversed rapidly and efficiently using a combination of data partitioning and table look ups. In an exemplary embodiment, the invention is employed...
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6377999 |
Firmware and software protocol parser
An improved method and computer to parse a data stream comprising a series of command strings is disclosed. The method provides superior performance in terms of balance between processor cycle...
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6363470 |
Circular buffer management
Data processing apparatus 10 supporting circular buffers CB includes address storage ARx for holding a virtual buffer index and offset storage BOFxx for holding an offset address. Circular buffer...
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6363469 |
Address generation apparatus
An address generation apparatus for generating a first address and a second address includes a first register for storing a first reference address; a second register for storing a second reference...
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6363471 |
Mechanism for handling 16-bit addressing in a processor
A processor includes an address generation unit (AGU) which adds address operands and the segment base. The AGU may add the segment base and the displacement while other address operands are being...
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6360308 |
Buffer controller
A method and apparatus for accessing successive memory locations without the need for multiple index register writes and without the need for a wide address bus from the controller into a memory...
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6341325 |
Method and apparatus for addressing main memory contents including a directory structure in a computer system
A system for accessing contents of the directory structure in a computing system having a CPU and implementing indirectly addressable main memory via a first directory structure included in the...
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6327508 |
Programmable state machine
A programmable state machine provides a capability of dynamically changing state-machine functions. State machine programming may be accomplished dynamically by a processor through a plurality of...
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6314507 |
Address generation unit
An Address Generation Unit (AGU) for a processor such as Digital Signal Processor that includes a data memory addressable to obtain X and Y operands and a program decoder. The AGU is connected to...
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6314504 |
Multi-mode memory addressing using variable-length
A processor architecture and associated method improve efficiency of memory accesses and thereby reduces power consumption. New addressing modes reduce most instructions to one or two bytes in...
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6314506 |
Method and apparatus for determining a next address within a binary search algorithm
A method and apparatus are presented for implementing the next-address determination within a binary search algorithm. A binary search algorithm searches for a compared within a one dimensional...
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6298429 |
Memory address generator capable of row-major and column-major sweeps
An improved method and structure for generating addresses of a memory array facilitates the testing of a memory cell by generating the address of any adjacent memory cell to the memory cell under...
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6289432 |
Sharing segments of storage by enabling the sharing of page tables
Segments of storage of a computer system are shared among any number of users at varying virtual addresses. The virtual addresses can be in the same address space or different address spaces. The...
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6289418 |
Address pipelined stack caching method
The present invention uses a stack management unit including a stack cache to accelerate data retrieval from a stack and data storage into the stack. In one embodiment, the stack management unit...
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6289428 |
Superscaler processor and method for efficiently recovering from misaligned data addresses
A superscalar processor and method are disclosed for efficiently recovering from misaligned data addresses. The processor includes a memory device partitioned into a plurality of addressable memory...
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6272615 |
Data processing device with an indexed immediate addressing mode
A data processing device is provided with an indexed-immediate addressing mode for processing streams of data. An instruction register 900 receives an instruction for execution. Decoding circuitry...
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6266756 |
Central processing unit compatible with bank register CPU
When data that does not fill a bit size (32 bits) of a first register is stored in the first register, 8-bit data is supplied from a second register or a first constant generator to unfilled higher...
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6266757 |
High speed four-to-two carry save adder
A circuit for adding two or more numbers and generating a sum and carry output is disclosed. The adder circuit receives two or more numbers to be added together. The adder circuit includes a number...
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6266747 |
Method for writing data into data storage units
A computer system merges data variables to be written into the same memory address. The data variables are merged by generating mask bits corresponding to the positions of the data variables within...
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6263353 |
Method and apparatus for converting between different digital data representation formats
A method and apparatus for converting digital data representations, such as network addresses of different computer networks. Input data, which in one embodiment includes a hexadecimal network...
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6249827 |
Method for transferring data associated with a read/write command between a processor and a reader circuit using a plurality of clock lines
A memory circuit with glitch-less transfer of timing information. In one embodiment, the invention is a memory circuit including a controller, multiple loads, a command link communicatively...
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6247107 |
Chipset configured to perform data-directed prefetching
A chipset is configured to communicate between one or more processors and other components of the computer system, including a main memory. The chipset communicates read memory operations initiated...
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6243767 |
System for register partitioning in multi-tasking host adapters by assigning a register set and a unique identifier in each of a plurality of hardware modules
An integrated circuit includes a sequencer module that executes firmware command lines and a plurality of hardware I/O bus interface modules. The plurality of hardware modules operates...
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6237075 |
System and method for generating pseudo-random codes
The invention provides a volatile or non-volatile memory and a latching circuit wherein data held in a first memory location is used to address the next memory location, in addition to providing a...
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6226733 |
Address translation mechanism and method in a computer system
An improved address translation method and mechanism for memory management in a computer system is disclosed. A fast physical address is generated in parallel with a fully computed...
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6212616 |
Even/odd cache directory mechanism
The index field of an address maps to low order cache directory address lines. The remaining cache directory address line, the highest order line, is indexed by the parity of the address tag for...
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6209076 |
Method and apparatus for two-stage address generation
The present invention is an apparatus and method for two-stage address generation that uses pipelining to avoid one level of latency in certain address-generation situations. The first level of the...
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6205531 |
Method and apparatus for virtual address translation
A method and apparatus for efficiently translating virtual to physical addresses is provided. An embodiment of the apparatus includes a TLB descriptor table that includes a series of TLB...
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6205511 |
SDRAM address translator
A buffer manager divides a memory space into a plurality of buffers. Each buffer occupies a plurality of sequential memory locations. The sequential memory locations include a start and an end...
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6202140 |
Memory addressing system and method therefor
An improved memory addressing system has a CPU having both an address bus and a multiplexed data/address bus. A reduced PIN out companion chip is coupled to the multiplexed data/address bus for...
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6195737 |
Method and apparatus for relative addressing of tiled data
The invention provides a method and apparatus that provides for a determination of a memory address for an object coordinate in a non-linear addressing scheme. To minimize computation complexity,...
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6192458 |
High performance cache directory addressing scheme for variable cache sizes utilizing associativity
To avoid multiplexing within the critical address paths, the same address field is employed as a index to the cache directory and cache memory regardless of the cache memory size. An increase in...
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6189062 |
Apparatus and method for address translation in bus bridge devices
A bridge translates addresses between a first bus and a second bus, with a larger address space capability. The bridge stores "high address" information and combines that information with address...
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