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6560694 Double prefix overrides to provide 16-bit operand size in a 32/64 operating mode  
A processor supports an operating mode in which the default address size is greater than 32 bits and the default operand size is 32 bits. The default address size may be nominally indicated as 64...
6560687 Method of implementing a translation lookaside buffer with support for a real space control  
To support a new processor control bit, the Real Space Control (RSC) bit, in a processor system with an existing translation lookaside buffer, an existing control bit, the Private Space bit, in the...
6560689 TLB using region ID prevalidation  
A prevalidation content addressable memory, CAM, is used to pre-decode a virtual address region extension and enable it for use by a translation look-aside buffer, TLB. The prevalidation CAM...
6553455 Method and apparatus for providing passed pointer detection in audio/video streams on disk media  
A method and apparatus for providing passed pointer detection in audio/video streams on disk media. The present invention sets up an audio/video stream on a disk drive, uses read and write commands...
6549979 Address mapping in mass storage device mounting system  
A technique is provided for mapping mass storage device addresses to mass storage devices mounted in a mass storage device mounting system. The mounting system may include a single type of chassis...
6549998 Address generator for interleaving data  
An interleaver generates a valid interleaved data address for each iteration i of the mapping by the interleaver without employing a multiplication operation. The interleaver includes an address...
6539452 Semiconductor redundant memory provided in common  
The present invention relates to a semiconductor memory having a pre-fetch structure. In such memory, an odd address cell array is provided with an odd address redundant cell array, and an even...
6539470 Instruction decode unit producing instruction operand information in the order in which the operands are identified, and systems including same  
An instruction decode unit is described including circuitry coupled to receive an instruction. The instruction identifies multiple operands, one of which is a destination operand. The circuitry...
6532529 Microcomputer including flash memory overwritable during operation and operating method thereof  
A microcomputer includes a flash memory, a central processing unit, a plurality of storage devices, and an address predecoder. The predecoder is configured to switch between a first memory mapping...
6532556 Data management for multi-bit-per-cell memories  
A multi-bit-per-cell memory reduces the effect of defects and data errors by scrambling data bits before writing data. The scrambling prevents storage of consecutive bits in the same memory cell....
6512742 System for data transmission across a link aggregation  
A method and system are disclosed for balanced transmitting of data across a link aggregation of k links in a network, where k is not a power of 2, where data is specified by frames each having a...
6510507 Page address look-up range ram  
A Page Address Look-up Range RAM is disclosed which allows for individual comparisons to be made on a number of consecutive addresses. The upper bits of the bus address 410 (often representing a...
6505288 Matrix operation apparatus and digital signal processor capable of performing matrix operations  
A digital signal processor capable of performing matrix operations, by which it is possible to use a method of matrix representation for the instruction level of the digital signal processor in...
6505271 Increasing priority encoder speed using the most significant bit of a priority address  
A method of generating a priority address using a priority encoder that includes the steps of: (1) providing a plurality of match signals from a CAM cell memory array to the priority encoder, (2)...
6496910 Method and device for loading instruction codes to a memory and linking said instruction codes  
A method for loading instruction codes to a first memory and linking said instruction codes is proposed, whereby at least one instruction code has as parameter an address which during a loading...
6493814 Reducing resource collisions associated with memory units in a multi-level hierarchy memory system  
A system and method for reducing resource collisions associated with memory units. Resource collisions may be reduced in part by a hash that combines the number N bits in the bank selector field...
6487650 Process-loop monitor system and method  
Methods of maintaining a record of a samples of a time-dependent variable in a computer memory whereby any period of time extending backward from the present, having a duration between a...
6480874 Power saving method for performing additions and subtractions and a device thereof  
A power saving device and method for either adding or subtracting a constant from an operand, by checking a logic value of a portion of the operand and deciding whether to activate a multi-bit...
6477635 Data processing system including load/store unit having a real address tag array and method for correcting effective address aliasing  
A data processing system including a processor having a load/store unit and a method for correcting effective address aliasing. In the load/store unit within the processor, load and store...
6467035 System and method for performing table look-ups using a multiple data fetch architecture  
A novel table look-up/indirect addressing system and method uses a dual fetch Harvard architecture to accomplish one full table look-up access per instruction cycle. The offset access fetch, the...
6467014 Automatic mapping and efficient address translation for multi-surface, multi-zone storage devices  
Automated address mapping is achieved by a system and methodology which automatically reacts to changes in the disk configuration. Prior to utilizing the disk, disk configuration information is...
6463514 Method to arbitrate for a cache block  
A method of arbitrating between cache access circuits (i.e., load/store units) by stalling a first cache access circuit in response to detection of a conflict between a first cache address and a...
6463518 Generation of memory addresses for accessing a memory utilizing scheme registers  
An circuit arrangement and method utilize scheme registers to select among a plurality of indirect address registers from which to retrieve a stored memory address. Rather than identifying within...
6456891 System and method for transparent handling of extended register states  
A system and method for transparent handling of extended register states. A set of additional registers, or an extended register file, is added to the base architecture of a microprocessor. The...
6457113 Memory management apparatus in a multi-channel signal processor  
A multi-channel signal processing apparatus comprises a memory unit, a signal processing unit for single-channel implementing predetermined signal processing using a memory region of the memory...
6453405 Microprocessor with non-aligned circular addressing  
A data processing system having a central processing unit (CPU) with address generation circuitry for accessing a circular buffer region in a non-aligned manner is provided. The CPU has an...
6449706 Method and apparatus for accessing unaligned data  
A method and apparatus for accessing data from a memory. The method includes masking off a portion of a first memory address, and accessing a first unit of data corresponding to the first memory...
6446187 Virtual address bypassing using local page mask  
A cache with a translation lookaside buffer (TLB) that reduces the time required for retrieval of a physical address from the TLB when accessing the cache in a system that supports variable page...
6442671 System for priming a latch between two memories and transferring data via the latch in successive clock cycle thereafter  
A system for transferring data in a single clock cycle between a digital signal processor (DSP) and an external memory unit and method of same. The system includes a data transfer element coupled...
6438674 Hash Cam having a reduced size memory array and its application  
A hash CAM is provided with a hashing unit and a memory array. The hashing unit is designed to generate an n-bit index in response to an m-bit input, where n and m are positive integers, and n is...
6430684 Processor circuits, systems, and methods with efficient granularity shift and/or merge instruction(s)  
A method of operating a processor (30). The method comprises a first step of fetching an instruction (20). The instruction includes an instruction opcode, a first data operand bit group...
6430672 Method for performing address mapping using two lookup tables  
A method for performing address mapping for a memory within a computer system is disclosed. The memory is organized in multiple of memory banks, and each memory bank is identified by a respective...
6430671 Address generation utilizing an adder, a non-sequential counter and a latch  
An integrated circuit, e.g. an AC '97 conforming audio codec, includes a digital filter and gain module including multiple channels of gain control and multiple channels of digital filtering. A...
6427200 Multiple changeable addressing mapping circuit  
A multiple changeable addressing mapping circuit is disclosed for converting an input logic address of a field array in a data array into an output physical address. The circuit has multiple...
6425065 Tag RAM with selection module for a variable width address field  
A tag RAM is coupled to an address bus that is adapted to carry a variable width address field. The tag RAM includes a memory section coupled to the address bus and a comparator coupled to the...
6425067 Systems and methods for implementing pointer management  
A system and method of compressing memory for efficiently searching the memory. Values are assigned to initial memory locations and these values are logically combined to form a first group of...
6421825 Register control apparatus and method thereof for allocating memory based on a count value  
In a register controlling apparatus, whenever a routine is run, a register logicalal address, and the values of a local register pointer and a local register counter are selectively added, and...
6411552 Data processing system, block erasing type memory device and memory medium storing program for controlling memory device  
A data processing system is provided with a flash memory including a plurality of blocks and capable of erasing stored data collectively in units of block and a memory control unit for accessing...
6408374 Hashing method and apparatus  
A hashing method and apparatus uses a hash function that can be modified in real time by a hash control code. The hash function involves the combining together of multiple bit-shifted versions of a...
6405298 Linear address generator and method for generating a linear address using parallel computations and a single cycle algorithm  
A high-speed linear address generator (LAGEN) and method for generating a linear address are disclosed, which generator is operable to generate a linear address very quickly. In a preferred...
6401185 Method and apparatus for accessing paged objects using a fast division technique  
A fast division technique is provided to calculate the address of a slot in a paged object, when the slot is located on a different page than the beginning of the object. The fast division...
6400293 Data compression system and method  
A system for encoding data is provided. The system includes a number parser that breaks down a field that has many digits into a set of data strings that each has a fixed number of digits. A...
6397318 Address generator for a circular buffer  
This invention describes an apparatus and method for the fast and efficient generation of addresses for a circular buffer involving only addition. The invention uses as input the present address,...
6397324 Accessing tables in memory banks using load and store address generators sharing store read port of compute register file separated from address register file  
A very long instruction word (VLIW) processor typically requires a large number of register file ports due to the parallel execution of the sub-instructions comprising the VLIW. By splitting a...
6397326 Method and circuit for preloading prediction circuits in microprocessors  
A method and circuit is provided for preloading a branch prediction unit within a microprocessor. In one embodiment of the method, a branch history storage device such as branch history shift...
6397291 Method and apparatus for retrieving data from a data storage device  
A data retrieval system receives a data address identifying data to be retrieved. A portion of the received data address is communicated to a data storage device during a first clock cycle. The...
6393544 Method and apparatus for calculating a page table index from a virtual address  
A method and apparatus calculate a page table index from a virtual address. Employs a combined hash algorithm that supports two different hash page table configurations. A “short format” page tab...
6388586 Method for reversing the bits of a computer data structure  
The bits comprising a computer data structure are reversed rapidly and efficiently using a combination of data partitioning and table look ups. In an exemplary embodiment, the invention is employed...
6377999 Firmware and software protocol parser  
An improved method and computer to parse a data stream comprising a series of command strings is disclosed. The method provides superior performance in terms of balance between processor cycle...
6363470 Circular buffer management  
Data processing apparatus 10 supporting circular buffers CB includes address storage ARx for holding a virtual buffer index and offset storage BOFxx for holding an offset address. Circular buffer...