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6754649 Apparatus and method for storing data in a storage medium, while saving storage areas which are used for holding a data path name and become necessary in response to the storing of data  
An apparatus and method for storing and retrieving data files from a storage medium are disclosed. A storage medium stores one or more data files and address information showing the path of each...
6751718 Method, system and computer program product for using an instantaneous memory deficit metric to detect and reduce excess paging operations in a computer system  
A method, system and computer program product for detecting when insufficient RAM is available in a computer system, and estimating the additional RAM needed to avoid excess paging. The invention...
6745316 Data processing system  
A data processing system is disclosed. The system includes a control command storage device, a data storage device, an address pointer, a multi-level signal decoder and a data processing unit. The...
6745284 Data storage subsystem including a storage disk array employing dynamic data striping  
A data storage subsystem including a storage disk array employing dynamic data striping. A data storage subsystem includes a plurality of storage devices configured in an array and a storage...
6742101 Scalable and flexible method for address space decoding in a multiple node computer system  
A multi-node computer system includes a plurality of I/O nodes, CPU nodes, memory nodes, and hybrid nodes connected via an interconnect. A CPU node or an I/O node issues a request. An address...
6742112 Lookahead register value tracking  
Apparatus and methods to track a register value. A microprocessor can include a first register, a control circuit, and an adder. The first register can store a tracked register value. The control...
6742113 Microprocessor with EIT, processing capability, and EIT processing method  
A microprocessor connected to external memory storing a reset process program and an exception, interrupt, or trap (EIT) processing program, has an internal memory for storing an application...
6742105 Method and system for range matching  
A range match circuit is disclosed for fast compare of an incoming address by partitioning the incoming address into fields. In one embodiment, a 16-bit incoming address is divided into quarterly...
6735682 Apparatus and method for address calculation  
A dual-cycle address generation unit is described to generate linear addresses. The dual-cycle address generation unit includes a first adder to add a product of an index and a scaling factor to...
6732258 IP relative addressing  
A processor supports instruction pointer (IP) relative addressing in at least one operating mode of the processor. For example, in some implementations, IP relative addressing is supported in an...
6732252 Memory interface device and memory address generation device  
A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including a plurality of output areas; and a control section for...
6732192 Disc recording scheme for enabling quick access to disc data  
A system for recording data to a disc shaped record medium. The data is recorded according to a universal disc format employing a hierarchical file system, and data within the hierarchical...
6732248 System and method for ghost offset utilization in sequential byte stream semantics  
A system and method for releasing storage space at the beginning of a byte stream while maintaining sequential byte stream semantics is provided. A ghost offset is initialized when a file is...
6728861 Queuing fibre channel receive frames  
A frame receive queue may perform disassembly and validation operations on frames received by a node in a Fiber Channel network. The frame receive queue may store information used for later...
6725353 Input/output register programming system and method  
An input/output register programming system that uses a set transmission value. The input/output register programming system includes an address decoder, a transmission setting register, a...
6725298 Method and system for filter-processing by ensuring a memory space for a ring-buffer in digital signal processor  
A method of managing ring-buffer memory space in a digital signal processor when processing a filter, includes releasing ring-buffer memory space previously reserved for ring-buffer data upon...
6725366 System and method for 32 bit code branching to 64 bit targets  
A system and method for converting 32 bit addresses into 64 bit addresses and enabling the 32 bit address to include a region index. The region index is stored in low order bits of the 32 bit...
6725289 Transparent address remapping for high-speed I/O  
A subsystem that is able to address a second memory region initiates I/O requests directed to a device that is able to address a first memory region that is different from the second memory...
6721849 Front end system having multiple decoding modes  
Embodiments of the present invention provide a pre-decoder in a front-end system provided between an instruction cache and a decoder. The front-end system may toggle between two modes of...
6715059 Methods and systems for a shared memory unit with extendable functions  
Systems and methods are described for an enhanced shared memory unit. Embodiments of methods presented may include permitting a plurality of central processing units to simultaneously read data...
6715058 Apparatus and method for a sorting mode in a direct memory access controller of a digital signal processor  
In order to sort signal group elements organized in blocks in a time-division multiplex protocol into frames of related elements, an address unit addresses the first element in each of the element...
6711664 Method and system for decoding a row address to assert multiple adjacent rows in a memory structure  
A memory array or structure and method for decoding a read address to facilitate simultaneous reading of successive rows. The memory includes row decoders in the form of decoding logic for...
6708266 Central processing unit and system counting instructions in a queue storage and outputting a fetch request when the count value is 0 or 1 to produce a next instruction address output  
The central processing unit is provided with an instruction queue storage section. This central processing unit is made of a memory, such as FIFO memory, that adopts first-in first-out method. A...
6704833 Atomic transfer of a block of data  
A method for transferring data between a processor and a memory includes (A) executing, at the processor, an instruction that includes (i) a specifier of a location in a storage resource local to...
6694420 Address range checking circuit and method of operation  
An address range checking circuit capable of determining if a target address, A[M:0], is within an address space having 2N address locations beginning at a base address location, B[M:0], is...
6694422 Semiconductor memory device having adjustable page length and page depth  
A semiconductor device with adjustable number of pages and page depth is disclosed. The semiconductor device includes multiple memory cell array blocks, a page control circuit for generating a...
6694407 Cache memory with data transfer control and method of operating same  
A cache memory (35) has a logical organisation in which its memory space is divided into sub-sections or partitions (P). This permits different data objects to be allocated to different partitions...
6687782 Method and implementation for addressing and accessing an expanded read only memory (ROM)  
A ROM is provided with sufficient input address terminals for receipt of a unique address for each data storage location, even though the number of ROM input addresses exceeds the capacity of the...
6681313 Method and system for fast access to a translation lookaside buffer  
In a system for conducting virtual address translation in a virtual memory system and implementing a table such as a Translation Lookaside Buffer, a system and method enabling quicker access to...
6675282 System and method for employing a global bit for page sharing in a linear-addressed cache  
A system and method for storing only one copy of a data block that is shared by two or more processes is described. In one embodiment, a global/non-global predictor predicts whether a data block,...
6666383 Selective access to multiple registers having a common name  
Among the embodiments of the present invention is a processor (22) having a number of registers in a register bank (50). The registers include a general purpose register (52a) and a stack pointer...
6665770 Device and method for updating a pointer value by switching between pointer values  
In order to enable a pointer register device including registers called shadow registers to conduct updating operation rapidly by arithmetic operation of a pointer value between the registers, a...
6658547 Method and apparatus for specifying address offsets and alignment in logic design  
A method for asserting an address alignment of an address for a memory-mapped device in a logic design is disclosed. An align primitive comprising an alignment size port, an input address port and...
6654646 Enhanced memory addressing control  
A processing or control system having arrangements for separately and simultaneously generating instruction addresses and data addresses having two bus systems for accessing instruction and data...
6651157 Multi-processor system and method of accessing data therein  
A multi-processor system (10) includes a plurality of processors (12). Each processor (12) has an integrated memory (16) operable to provide, receive, and store data. Each processor (12) also...
6651160 Register set extension for compressed instruction set  
Systems and methods for extending register addresses in compressed instruction sets are capable of executing extended register instructions that supplement the bits needed to address registers....
6647483 Address translation circuit for processors utilizing a single code image  
A circuit comprising a processor and a translation circuit. The processor may be configured to present a first address. The translation circuit may be configured to (i) determine a mask and an...
6647484 Transpose address mode in general purpose DSP processor  
The present invention provides a register-indirect addressing mode using modulo arithmetic to transpose addresses for digital processing systems. The preferred systems and methods permit direct...
6643761 Address generation unit and digital signal processor (DSP) including a digital addressing unit for performing selected addressing operations  
An address generation unit (AGU) and a digital signal processor (DSP) including such an AGU are disclosed. The AGU (3) has a register file (4) providing order (R), stage (S), and displacement (N)...
6640296 Data processing method and device for parallel stride access  
A method and apparatus for accessing data elements of an N-element data block on N memory locations distributed over Q memory modules via Q parallel accesses. The Q memory modules are addressable...
6636938 Sound generator  
A sound generator, capable of improving a DRAM download speed and reducing power consumption when operating a DRAM download by applying a dedicated download logic, may increase the download speed...
6629219 Method and apparatus for providing highly programmable memory mapping and improved interleaving  
A method and apparatus for providing highly programmable memory mapping and improved interleaving includes a system address chip that maps a received memory transaction address to an intermediate...
6625718 Pointers that are relative to their own present locations  
An auto (i.e., self)-relative pointer (114, 115) in a data structure (103) of a computer (100) defines a pointed-to location (106, 107) by means of an offset from its own location (104, 105). The...
6625719 Processing devices with improved addressing capabilities systems and methods  
A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation...
6622208 System and methods using a system-on-a-chip with soft cache  
A soft cache system compares tag bits of a virtual address with tag fields of a plurality of soft cache register entries, each entry associated with an index to a corresponding cache line in...
6606688 Cache control method and cache controller  
A cache controller stores pre-set variables for pre-fetch block size and stride value. A cache controller receives an access request for the main memory from the processor, and generates a...
6604184 Virtual memory mapping using region-based page tables  
The present invention is a method and apparatus to map virtual memory space. A region register file provides a region identifier for a virtual address in the virtual memory space. The virtual...
6601158 Count/address generation circuitry  
According to one embodiment of the invention, an apparatus that includes a first and second counter both including a count computation circuit and an upper bound circuit. The output of the upper...
6598144 Arrangement for limiting access to addresses by a consumer process instigating work in a channel adapter based on virtual address mapping  
An operating system resource, configured for establishing communications between consumer processes configured for generating respective work notifications and a host channel adapter configured...
6587929 Apparatus and method for performing write-combining in a pipelined microprocessor using tags  
A tag-based write-combining apparatus in a microprocessor. The apparatus includes a register that stores the store address of the last write-combinable store passing through the store stage of the...