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6915393 Method and apparatus for physical memory partitioning  
The disclosed embodiments relate to a device for generating physical addresses in a multi-processor computer system. The computer system may be adapted to support multiple physical memory...
6912643 Method of flexibly mapping a number of storage elements into a virtual storage element  
The present invention provides an architecture and method for increasing the performance and resource utilization of networked storage architectures by use of hardware-based storage element...
6912616 Mapping addresses to memory banks based on at least one mathematical relationship  
One embodiment of the invention is a memory controller that maps a received address to a memory location in a plurality of memory banks, the memory controller comprising: circuitry for calculating...
6912645 Method and apparatus for archival data storage  
Data storage techniques particularly well-suited for use in archival data storage are disclosed. In one aspect of the invention, a data block is processed to generate an address as a function of...
6907511 Reducing transitions on address buses using instruction-set-aware system and method  
An instruction-set-aware method for reducing transitions on an irredundant address bus comprises receiving a first address for communication to a memory on an irredundant address bus. The method...
6901501 Data processor  
In a memory access process, by identifying the types of memories that can be activated without reducing operating speed and by reducing power consumption, a data processor capable of operating at...
6895488 DSP memory bank rotation  
An apparatus comprising a memory, a plurality of modules, an address translation unit and a controller. The memory may be arranged as a plurality of memory banks. Each of the plurality of modules...
6889307 Integrated circuit incorporating dual organization memory array  
A memory organization supports a basic page size and an extended page size. A certain portion of its memory cells are dual-addressable memory cells which may be used to provide the additional...
6886088 Memory that allows simultaneous read requests  
The present invention is directed to a memory that allows two simultaneous read requests with improved density. In an aspect of the present invention, a memory module includes at least two primary...
6883171 Dynamic address windowing on a PCI bus  
A multi-tasking operating system and method updates PCI address values in an extension register to ensure that various threads utilize the correct values when accessing peripheral PCI devices....
6883082 Central dynamic memory manager  
A circuit generally comprising a memory and a core module is disclosed. The memory may be configured as (i) a first stack having a plurality of index pointers and (ii) a table having a plurality...
6883072 Memory system and method of using same  
A memory system and method of using same are provided. In one embodiment of the present invention, the memory system may include a plurality of logic sections that may be used to facilitate...
6880022 Transparent memory address remapping  
A computer has a hardware memory arranged into portions that are separately addressable using first identifiers, which are represented using a first number of address bits. A subsystem that is...
6880065 Memory management method and system thereof  
A method and system thereof for managing a computer system memory, where the memory is structured as contiguous memory chunks, each chunk having a header. A chunk header includes a first offset...
6877069 History-based carry predictor for data cache address generation  
An address translation logic and method for generating an instruction's operand address. The address generation logic includes an address generation circuit having adders that perform partial sum...
6877161 Address calculation of invariant references within a run-time environment  
Efficient address calculation of invariant reference within a run-time environment is attained by a self-relative numeric reference format for run-time storage of references. A self-relative...
6877082 Central processing unit including address generation system and instruction fetch apparatus  
A disclosed address generation system includes a decrementer and a multiplexer. The decrementer produces a decremented address signal by subtracting a first integer value from an incremented...
6874081 Selection of link and fall-through address using a bit in a branch address for the selection  
A link address/sequential address generation circuit is provided for generating a link/sequential address. The circuit receives the most significant bits of at least two addresses: a first address...
6871262 Method and apparatus for matching a string with multiple lookups using a single associative memory  
Methods and apparatus are disclosed for matching a string with multiple lookups using a single associative memory, such as, but not limited to binary and ternary content-addressable memories...
6868489 Carry generation in address calculation  
Embodiments are provided in which the generation of a carry of a sum of two numbers can be implemented by adding only some most significant bits of the two numbers and assuming that the sum of the...
6865659 Using short references to access program elements in a large address space  
One embodiment of the present invention provides a system that accesses a desired element during execution of a program. During operation, the system receives a reference to the desired element....
6851039 Method and apparatus for generating an interleaved address  
In the method of generating an interleaved address, each 2^i mod (p−1) value for i=0 to x−1 is stored. Here, p is a prime number dependent on a block size K of a data block being processed and x...
6851041 Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor  
A pipelined data processing unit includes an instruction sequencer and n functional units capable of executing n operations in parallel. The instruction sequencer includes a random access memory...
6845439 Method and system for accessing an expanded SCB array  
A method for accessing hardware I/O control blocks, which are stored in an hardware I/O control block array, by a parallel SCSI host adapter addresses one page in a plurality of pages of the...
6845440 System for preventing memory usage conflicts when generating and merging computer architecture test cases  
A system for detecting/avoiding memory usage conflicts when generating and merging multi-threaded software test cases. Initially, a test case generator is given a unique segment of memory which it...
6839827 Method, system, program, and data structures for mapping logical blocks to physical blocks  
Disclosed is a method, system, program, and data structure for a storage controller to map logical blocks to physical storage blocks. The storage controller is in communication with at least one...
6836835 Combined logic function for address limit checking  
The present invention relates to central processing units in computer systems, and in particular, it relates to a method and a respective hardware implementation of an add operation and a subtract...
6834335 System and method for reducing transitions on address buses  
An encoder and decoder provide coding of information communicated on buses. The encoder and decoder may use various combinations of techniques to reduce switching activity on an address bus.
6829694 Reconfigurable parallel look up table system  
A reconfigurable parallel look-up table system includes a memory; a plurality of look-up tables stored in the memory; a row index register for holding the values to be looked up in the look-up...
6826669 Multi-protocol memory lookup system and method  
A memory system includes a memory array for storing a plurality of data elements, the memory array comprising a plurality of memory blocks. In one embodiment, the data element are tag string data....
6826672 Capability addressing with tight object bounds  
A pointer representation includes a permission field to define capabilities of the system in processing the data to which an address in the pointer of representation points. Bounds of the memory...
6823442 Method of managing virtual volumes in a utility storage server system  
A method is provided to allow a system administrator of a utility storage server to provision virtual volumes several times larger than the amount of physical storage within the storage server. A...
6816959 Memory access system  
A memory access system is described which generates two memory addresses from a single memory access instruction which identifies a register holding at least two packed objects. In the preferred...
6813699 Speculative address translation for processor using segmentation and optional paging  
An improved address translation method and mechanism for memory management in a computer system is disclosed. A segmentation mechanism employing segment registers maps virtual addresses into a...
6813700 Reduction of bus switching activity using an encoder and decoder  
An encoder and decoder provide coding of information communicated on busses. The encoder and decoder may use various combinations of techniques to reduce switching activity on an address bus.
6804767 Method and system for automatic address table reshuffling in network multiplexers  
A method and system for storing and accessing associations between network addresses and ports within a network multiplexer. The method and system implement an address table containing indexed...
6801993 Table offset for shortening translation tables from their beginnings  
A virtual address is translated to a real address using one or more tables at varying levels. An entry of a table is indexed based in part on a table origin and a table offset. The virtual address...
6799261 Memory interface with fractional addressing  
A memory interface device (100) providing a fractional address interface between a data processor (104) and a memory system (102) and a method for retrieving intermediate data values from a memory...
6785798 Method and system for circular addressing with efficient memory usage  
An apparatus generates addresses for circular address buffers in a memory, in which a higher boundary of a circular buffer is implied from the current address. This approach is applied alone, and...
6785743 Template data transfer coprocessor  
The template data transfer coprocessor (TDTP) offloads block data transfer operations from a mediaprocessor. A uni-block template, program-guided template, an indirect template and queue-based...
6782447 Circular address register  
A device and corresponding programming instructions are provided that facilitate a circular addressing process. The device is configured to provide an address output that is constrained to lie...
6782445 Memory and instructions in computer architecture containing processor and coprocessor  
In a computer system, a first processor, a second processor for use as a coprocessor to the first processor, a memory, a data buffer for buffering data to be written to or read from the memory in...
6779098 Data processing device capable of reading and writing of double precision data in one cycle  
A data processing device includes a memory system capable of a plurality of simultaneous accesses, a plurality of address generators each generating an address for accessing the memory system, an...
6779100 Method and device for address translation for compressed instructions  
A computer system for storing corresponding instruction blocks in a compressed form in a main memory and in an uncompressed form in an instruction cache. The instruction cache line addresses for...
6775758 Buffer page roll implementation for PCI-X block read transactions  
A computer system containing logic for processing a read block transaction from a PCI-X device. A technique is also disclosed for processing a read block transaction from a PCI-X device. The...
6769055 Two-part memory address generator  
A memory address generator for a multiport data communication system storing received data packets in a memory having a plurality of storage areas. The data communication system has a plurality of...
6766436 Data processor having an address translation circuit  
In the address translation, there is a region in which the translation having a common regularity is possible into a plurality of regions, and a region in which such a translation is not possible....
6766433 System having user programmable addressing modes and method therefor  
A system (10) implements user programmable addressing modes in response to control information contained within an input address. Encoded control information stored in a plurality of user...
6760830 Modulo addressing  
In one embodiment, a modulo addressing unit for a processor is described that includes a plurality of adders to generate an uncorrected target module address and at least one corrected target...
6757789 Apparatus and method for maximizing information transfers over limited interconnect resources  
The present invention provides various techniques for optimized transfer of information in electronic systems involving memory devices to improve data bandwidth. The invention offers solutions to...