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7107430 Mechanism to reduce the cost of forwarding pointer aliasing  
Short-quasi-unique-identifiers (SQUIDs) are generated and assigned to the data objects stored in memory. Pointers to a particular data object contain the data object's assigned SQUID. If a data...
7107429 Data access in a processor  
A data processor comprising: a register memory comprising an array of memory cells, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the cell...
7103751 Method and apparatus for representation of an address in canonical form  
A method and apparatus for representing an address in canonical form. The address is received and an error indicator is computed according to whether the address is received in a correct canonical...
7100019 Method and apparatus for addressing a vector of elements in a partitioned memory using stride, skip and span values  
A system and method for calculating memory addresses in a partitioned memory in a processing system having a processing unit, input and output units, a program sequencer and an external interface....
7096342 Flexible LUN/LBA interface for content addressable reference storage  
An LUN/LBA interface is utilized to obtain the benefits of a content addressed storage (CAS) interface. Reference data is manipulated in a manner similar to a CAS system, where an object ID (OID)...
7093102 Code sequence for vector gather and scatter  
Gather and scatter operations are used when elements of a vector which may be operated on in parallel are not located at successive addresses in memory. Prior data processing systems required...
7093103 Method for referring to address of vector data and vector processor  
The object of the invention is to efficiently perform indirect index vector reference. An element register of a vector register or a scalar register specified in the “index” is divided into...
7089398 Address translation using a page size tag  
A method and system for resolving virtual addresses using a page size tag are described herein. In one embodiment, the method comprises translating a virtual memory address into physical memory...
7082509 Method and system for allocating memory during system boot to reduce operating system memory resource consumption at run-time  
A method and system for allocating memory during system boot to reduce operating system memory resource consumption at run-time. A memory heap comprising a portion of a computer system memory in...
7076584 Method and apparatus for interconnecting portions of circuitry within a data processing system  
A method and apparatus for interconnecting circuit portions (12, 14, 16, 18, 20) within a data processing system (10) using a master/slave interfaces (30–37, 134) which may be configured by way of...
7076596 Method of and apparatus for enabling a hardware module to interact with a data structure  
A method of enabling a hardware module to interact with a data structure is disclosed. The method comprises the steps of enabling the hardware module to determine an address of a data item...
7073047 Control chip and method for accelerating memory access  
A control chip and operating method for accelerating memory access that can be applied to a memory system whose memory read command actual address is read from a system bus in a number of...
7069398 Apparatus and method for de-interleaving the interleaved data in a coded orthogonal frequency division multiplexing receiver  
An apparatus and method having a de-interleaving memory and a controller is used for de-interleaving interleaved data in a coded orthogonal frequency division multiplexing receiver. The controller...
7065625 Computer system, method, and program product for performing a data access from low-level code  
A computer system includes a register that is configured to contain a zero value. In response to a predetermined occurrence on the computer system, such as a hardware interrupt, the computer...
7062632 Method for controlling a central processing unit for addressing in relation to a memory and controller  
The present invention is based on the finding that free CPU operation code identifiers of a CPU or CPU operation code identifiers useable for any reason can be used to control supporting means...
7058789 System and method for packet storage and retrieval  
A network services processor receives, stores, and modifies incoming packets and transmits them to their intended destination. The network services processor stores packets as buffers in main and...
7058755 EEPROM emulation in flash memory  
An efficient emulation of EEPROM employing flash memory employs a fixed location for an address pointer in flash memory and such that an erase operation is required only once every nth update...
7058788 Dynamic allocation of computer memory  
A method for processing requests or commands for writing and reading to and from memory that has not been allocated and reserved for one or more volumes, and a method for establishing one or more...
7055017 Optical disk drive, method for formatting optical disk, and optical disk  
An optical disk drive for initializing an optical disk by dividing a recording area into zones and by assigning logical addresses to each of the zones. The disk drive includes a medium management...
7051184 Method and apparatus for mapping memory addresses to corresponding cache entries  
One embodiment of the present invention provides a system for mapping memory addresses to cache entries. The system operates by first receiving a memory request at the cache memory, wherein the...
7043601 Priority encoder circuit and method  
A system and method for high speed generation of a global address corresponding to the highest priority active matchline sense output signal received after a CAM search-and-compare operation is...
7043618 System for memory access in a data processor  
A data processor comprising: a register memory comprising an array of memory cells, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the cell...
7043623 Distributed memory computing environment and implementation thereof  
A Distributed Memory Computing Environment (herein called “DMCE”) architecture and implementation is disclosed in which any computer equipped with a memory agent can borrow memory from other...
7039789 Circular addressing algorithms providing increased compatibility with one or more higher-level programming languages  
Logic for circular addressing providing increased compatibility with higher-level programming languages accesses a base pointer pointing to a first element of an array including a number of...
7032097 Zero cycle penalty in selecting instructions in prefetch buffer in the event of a miss in the instruction cache  
A method and processor for selecting instructions in a prefetch buffer in the event of a miss in an instruction cache with a zero cycle penalty. A first, second and third hash may be performed on...
7032098 Data-driven type information processing apparatus and information processing method allowing for effective use of memory  
A data-driven type information processing apparatus includes at least a paired data generating unit, a memory control unit, and data memory. The memory control unit includes a pipeline register...
7024544 Apparatus and method for accessing registers in a processor  
The present invention is generally directed to an apparatus and method for accessing registers within a processor. In accordance with one embodiment, an apparatus and method are provided for a...
7017028 Apparatus and method for updating pointers for indirect and parallel register access  
An apparatus and method are provided for updating one or more pluralities of pointers (i.e. one or more vector pointers) which are used for accessing one or more pluralities of data elements (i.e....
7010666 Methods and apparatus for memory map generation on a programmable chip  
Methods and apparatus are provided for the automatic assignment of addresses for slave components to be implemented on a programmable chip. Slave components including peripheral components and...
7003647 Method, apparatus and computer program product for dynamically minimizing translation lookaside buffer entries across contiguous memory  
A method, apparatus and computer program product are provided for dynamically minimizing translation lookaside buffer (TLB) entries across contiguous memory. A page table with page table entries...
6996698 Blocking processing restrictions based on addresses  
Processing restrictions of a computing environment are filtered and blocked, in certain circumstances, such that processing continues despite the restrictions. One restriction includes an...
6990551 System and method for employing a process identifier to minimize aliasing in a linear-addressed cache  
A system and method for reducing linear address aliasing is described. In one embodiment, a portion of a linear address is combined with a process identifier, e.g., a page directory base pointer...
6985402 Programmable address generator  
A programmable address generator comprising at least one input for receiving a first digital address of a data word in a first memory, to be converted into a second digital address of this same...
6976149 Mapping technique for computing addresses in a memory of an intermediate network node  
A mapping technique allows a forwarding engine of an intermediate node to efficiently compute a starting address within an internal packet memory (IPM) configured to hold a packet received at the...
6973551 Data storage system having atomic memory operation  
A method and system for enabling a director to perform an atomic read-modify-write operation on plural bit read data stored in a selected one of a plurality of memory locations. The method...
6965980 Multi-sequence burst accessing for SDRAM  
Methods and apparatus for accessing memory locations in a memory device in different orders. In one implementation, a memory device includes: a memory array, including a plurality of memory...
6963823 Programmatic design space exploration through validity filtering and quality filtering  
Design spaces for systems, including hierarchical systems, are programmatically validity filtered and quality filtered to produce validity sets and quality sets, reducing the number of designs to...
6952762 Data storage device with overlapped buffering scheme  
A data storage device is disclosed that, in response to a data output request, outputs stored data beginning with a selected output start address. The disclosed data storage device is...
6950922 Data extraction/insertion method and device in digital signal processor  
A data extraction/insertion device in a digital signal processor and a method thereof are provided. The data extraction/insertion method is performed in a digital signal processor including a...
6948005 Peripheral device for programmable controller  
A storage unit stores ranges of devices allocated for each sequence program. A device range checking unit sequentially extracts device notations indicating consecutive areas and commands...
6941445 Resampling address generator  
A resampling address generator updates period data in a resampling period address register when the periods of input and output clocks are not stable, and generates a read address by supplying the...
6934827 Method and apparatus for avoiding cache line collisions between an object and corresponding object table entries  
One embodiment of the present invention provides a system that facilitates avoiding collisions between cache lines containing objects and cache lines containing corresponding object table entries....
6934817 Controlling access to multiple memory zones in an isolated execution environment  
The present invention provides a method, apparatus, and system for controlling memory accesses to multiple memory zones in an isolated execution environment. A processor having a normal execution...
6931508 Device and method for information processing  
In an information processing device, a first address adder generates a first address representing a target for write of data or a storage location of data to be read. A second address adder...
6925547 Remote address translation in a multiprocessor system  
A method of performing remote address translation in a multiprocessor system includes determining a connection descriptor and a virtual address at a local node, accessing a local connection table...
6922766 Remote translation mechanism for a multi-node system  
A remote translation mechanism for a multi-node system. One embodiment of the invention provides a method for remotely translating a virtual memory address into a physical memory address in a...
6918024 Address generating circuit and selection judging circuit  
An address generating circuit, in which address generation by a modulo addition is executed at high speed, is provided. The address generating circuit makes, a two input adder that adds an address...
6915396 Fast priority determination circuit with rotating priority  
The invention describes a system for and a method of creating and using dependencies to determine the order of servicing transaction requests in a multiple queue environment. When more than one...
6915407 Method and apparatus for a low latency source-synchronous address receiver for a host system bus in a memory controller  
A method and apparatus for a source synchronous address receiver for a system bus. In one embodiment, a flow-through between a system bus address input to a memory bus is controlled by two inputs:...
6915408 Implementation of thread-static data in multi-threaded computer systems  
One of the primary difficulties that result from using static variables in multi-threaded computer programs is that changes to a static variable made by one thread will be seen by all other...