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7325092 Apparatus and methods for a static mux-based priority encoder  
Apparatus and methods for an improved priority encoder using only static circuit components. Features and aspects hereof rely exclusively on static logic circuits exclusive ROM and other memory...
7315931 Method for managing an external memory of a microprocessor  
A method for managing an external memory of a microprocessor so that the external memory only contains one copy of a common area. By providing an address translator, mapping the page and the...
7308557 Method and apparatus for invalidating entries within a translation control entry (TCE) cache  
A method and apparatus for invalidating entries within a translation control entry (TCE) cache are disclosed. A host bridge is coupled between a group of processors and a group of adaptors. The...
7302524 Adaptive thread ID cache mechanism for autonomic performance tuning  
An apparatus and method for inhibiting data cache thrashing in a multi-threading execution mode through simulating a higher level of associativity in a data cache. The apparatus temporarily splits...
7299329 Dual edge command in DRAM  
A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of...
7296136 Methods and systems for loading data from memory  
According to an exemplary embodiment of the present invention, a method for loading data from at least one memory device includes the steps of loading a first value from a first memory location of...
7296029 Environmentally responsive oscillating circular affinity index  
Various embodiments of a method, apparatus and article of manufacture to manage an index are provided. A circular index, having an index size, is provided. The circular index stores information to...
7293139 Disk array system generating a data guarantee code on data transferring  
To correctly generate LAs even when out-of-order occurs. In a disk array system according to the present invention, a control unit includes: a host input/output unit that exchanges data and a...
7269711 Methods and apparatus for address generation in processors  
Methods and apparatus to generate addresses in processors are disclosed. An example address generator disclosed herein includes an adder to add a first address component and a second address...
7268591 Decode structure with parallel rotation  
A memory subsystem and a method of operating therefor. The memory subsystem includes a memory array having 2n locations. The memory subsystem includes an address decoder and rotation logic each...
7266651 Method for in-place memory interleaving and de-interleaving  
A method for in-place interleaving and de-interleaving of a memory includes, in one embodiment, generating a new address corresponding to a new location in the memory by performing a bit-wise XOR...
7266667 Memory access using multiple sets of address/data lines  
Methods and apparatus for accessing multiple memory arrays within a memory device using multiple sets of address/data lines are provided. The memory arrays may be accessed independently, using...
7260096 Method and router for forwarding internet data packets  
The Internet data defining destinations accessible by a router are partitioned into a portion containing the address search information and a portion containing forwarding option data. The address...
7260669 Semiconductor integrated circuits  
When a peripheral LSI has a memory space which is other than the memory space of a CPU, access is made without one of the memory spaces being aware of the other memory spaces. A flexible bus...
7257643 Method and apparatus to improve network routing  
A method and apparatus to route information in a network is described. A technique is described to search for routine information that uses a first technique on at least a portion of a first value...
7254670 System, method, and apparatus for realizing quicker access of an element in a data structure  
This disclosure generally relates to a processor configured to access an element in a data structure. The processor includes an element in a data structure having an array, an index, and a base...
7249226 Semiconductor system and memory sharing method  
A semiconductor system according to an embodiment of the present invention comprises a shared memory; a plurality of processing units each of which designates a memory size and a memory address,...
7243210 Extracted-index addressing of byte-addressable memories  
A microprocessor circuit useful for indexed addressing of byte-addressable memories includes word-length index, base address, and destination registers designated by an instruction. The...
7240179 System, apparatus and method for reclaiming memory holes in memory composed of arbitrarily-sized memory devices  
A system, apparatus, and method are disclosed for increasing the physical memory address space accessible to a processor, at least in part, by translating linear addresses associated with a memory...
7234039 Method, system, and apparatus for determining the physical memory address of an allocated and locked memory buffer  
Methods and systems are provided for determining the physical address of an allocated and locked memory buffer. An application program may request the allocation of a memory buffer. A virtual...
7234030 Table-based scheduler for FIFOs and the like  
A scheduler for a set of data packet storage devices (e.g., FIFOs) implements a scheduling algorithm embodied in a look-up table (LUT) that identifies the next FIFO to select for service based on...
7222040 Methods and apparatus for producing an IC identification number  
Methods and apparatus provide for: testing a static random access memory (SRAM) to obtain performance data on the SRAM; and using the performance data as at least a basis of a identification number.
7213127 System for producing addresses for a digital signal processor  
A system for generating addresses for a digital signal processor in which the program instructions include a code for accessing a memory associated with said processor. An address calculation...
7213123 Method and apparatus for mapping debugging information when debugging integrated executables in a heterogeneous architecture  
The present invention provides for the employment of a dynamic debugger for a parallel processing environment. This is achieved by dynamically updating mapping information at run-time in a mapping...
7210021 Cache control program  
A cache control program that reduces cache control load. The cache control programs functions as a multi-bind cache (MBC) manager of a file server. The MBC manager manages a cache memory as a...
7206919 Rapid partial configuration of reconfigurable devices  
A system and method for enabling rapid partial configuration of reconfigurable devices includes a configuration definition unit and a configuration loading unit. The configuration definition unit...
7206918 Address predicting apparatus and methods  
Apparatus and methods for addressing predicting useful in high-performance computing systems. The present invention provides novel correlation prediction tables. In one embodiment, correlation...
7203827 Link and fall-through address formation using a program counter portion selected by a specific branch address bit  
A link address/sequential address generation circuit is provided for generating a link/sequential address. The circuit receives the most significant bits of at least two addresses: a first address...
7194517 System and method for low overhead message passing between domains in a partitioned server  
A system and method for passing messages between domains with low overhead in a multi-node computer system. A CPU node in a sending domain issues a request to a memory node in a receiving domain...
7191307 Memory management unit technique to detect cross-region pointer stores  
A method for detecting an invalid pointer including a source component and a target component, involving selecting a virtual source memory address for the source component wherein the virtual...
7191309 Double shift instruction for micro engine used in multithreaded parallel processor architecture  
A method of operating a processor includes concatenating a first word and a second word to produce an intermediate result, shifting the intermediate result by a specified shift amount and storing...
7188231 Multimedia address generator  
Embodiments of the invention provide an automatic address generator that generates an address sequence directly using counters that count between predefined start and stop values in accordance...
7185173 Column address path circuit and method for memory devices having a burst access mode  
Column addresses are generated by a burst controller that includes respective latches for the three low-order bits of a column address. The two higher order bits of the latched address bits and...
7181591 Memory address decoding method and related apparatus by bit-pattern matching  
An address decoding method and related apparatus for deciding which section of a memory device a given address belongs. The memory device has a plurality of sections, each section has a plurality...
7178003 Data processing apparatus, data processing system, and access area control method  
An address converter has a base address register and address mask register for setting the start address and range, respectively, of a transparent mode access permitted area. By using the values...
7173452 Re-programmable finite state machine  
A re-programmable finite state machine comprising a content-addressable memory (“CAM”) and a read/write memory output array (“OA”). In operation, the CAM receives and periodically latches a status...
7174433 System and method for dynamically sharing media in a computer network  
A computerized method for sharing removable storage media in a network, the method comprising associating, in an index entry, a first piece of removable storage media in a first storage device...
7155558 Providing access to a raw data storage unit in a computer system  
A computer has access to a system-formatted data storage unit (DSU) containing a file system and to a raw DSU. A file within the file system constitutes a raw DSU mapping that facilitates access...
7154416 Adaptive control of codebook regeneration in data compression mechanisms  
Adaptive control of codebook regeneration in data compression mechanisms. In one implementation, the present invention provides a means controlling the frequency of codebook updates based on...
7143265 Computer program product memory access system  
A memory access system is described which generates two memory addresses from a single memory access instruction which identifies a register holding at least two packed objects. In the preferred...
7142479 Addressing data within dynamic random access memory  
A method for addressing dynamic random access memory, with providing a row address and a column address to addressing terminals of the memory, in intervals provided by a timing clock signal, to...
7130968 Cache memory architecture and associated microprocessor design  
A single memory element, which may consist of general purpose SRAM chips, is used to implement both tag and data cache memory functions, resulting in an efficient, low cost implementation of high...
7127710 Identifying pure pointers to disambiguate memory references  
In one embodiment, disambiguation of memory references, such as structure field accesses, of a computer program is performed. Disambiguation may be effected by identifying pure pointer variables...
7124278 Information processing device and method, program, data structure, and computer-readable recording medium  
Upon implementing a data registration into or a data retrieval from a data table (3) where first item data are registered along with corresponding second item data, there are used a first pointer...
7120779 Address offset generation within a data processing system  
A data processing system 2 is provided supporting address offset generating instructions which encode bits of an address offset value using previously redundant bits in a legacy instruction...
7117347 Processor including fallback branch prediction mechanism for far jump and far call instructions  
A method and apparatus are provided for processing far jump-call branch instructions within a processor in a manner which reduces the number of stalls of the processor pipeline. The processor...
7117341 Storing and selecting multiple data streams in distributed memory devices  
Prior art storage techniques have certain limitations, including requiring additional external resources to implement and not making use of all of the available storage space. A method and...
7110373 Apparatus and method for controlling memory for a base station modem  
An apparatus and a method for controlling memory in a base station modem supporting multi-users including a memory divided into logical blocks for supporting the multi-users, and a controller for...
7111148 Method and apparatus for compressing relative addresses  
A method and apparatus for compressing relative addresses and for storage of compressed relative addresses. A relative virtual address is computed in a particular stage of a processor pipeline and...
7111149 Method and apparatus for generating a device ID for stacked devices  
A method for generating a unique device ID for each addressable device in a stack of multiple addressable devices by encoding a device ID for one device in the stack and determining a device ID...