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7917707 Semiconductor device  
A semiconductor device includes a plurality of operating units, a controller that controls the plurality of operating units according to predetermined state transition, a first storage that stores...
7913061 Non-volatile memory and method with memory planes alignment  
A non-volatile memory is constituted from a set of memory planes, each having its own set of read/write circuits so that the memory planes can operate in parallel. The memory is further organized...
7908458 Ethernet controller  
A controller, in particular an Ethernet controller has a control unit operable to receive commands and data through an I/O interface; a plurality of registers arranged in a register block which is...
7904839 System and method for controlling access to addressable integrated circuits  
A circuitry access system for controlling access to addressable circuit elements of an integrated circuit. The circuitry access system includes a first storage element having a first listing of...
7886126 Extended paging tables to map guest physical memory addresses from virtual memory page tables to host physical memory addresses in a virtual machine system  
A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a...
7885205 Media access control (MAC) address management system and method  
A media access control (MAC) address management system, comprises logic configured to generate a MAC address for at least one network device of a computing device based on a MAC address of another...
7882332 Memory mapped register file  
A register system for a data processing system includes an address encoder that generates an encoded address based on a processor mode identifier and a register identifier and memory comprising...
7882331 Method and system for simultaneously supporting different block sizes on a single hard drive  
A method and system where a hardware platform such as a disk drive is formatted to the largest block length it is desired to read from or write to. Using commands, data can be accessed from the...
7873810 Microprocessor instruction using address index values to enable access of a virtual buffer in circular fashion  
A modular subtraction instruction for execution on a microprocessor having at least one register. The instruction includes opcode bits for designating the instruction and operand bits for...
7865692 Methods and apparatus for automated generation of abbreviated instruction set and configurable processor architecture  
A systematic approach to architecture and design of the instruction fetch mechanisms and instruction set architectures in embedded processors is described. This systematic approach allows a...
7861059 Method for testing and programming memory devices and system for same  
A method and system are provided for programming a plurality of memory devices arranged in parallel. In one embodiment of the present invention, the plurality of memory devices comprises first and...
7856635 Dynamic address windowing on a PCI bus  
A multi-tasking operating system and method updates PCI address values in an extension register to ensure that various threads utilize the correct values when accessing peripheral PCI devices....
7849284 Message memory for a communication protocol and method  
A message memory (1) with a flexible association between the message-object memories of the message memory (2) and the segments of a physical memory (3). The association is made through...
7840744 Rank select operation between an XIO interface and a double data rate interface  
In an aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) generating a first command and associated address of a first type that...
7836274 Method and system for combining page buffer list entries to optimize caching of translated addresses  
Certain aspects of a method and system for combining page buffer list entries (PBLEs) to optimize caching of translated addresses are disclosed. Aspects of a method may include encoding at least...
7836295 Method and apparatus for improving the resilience of content distribution networks to distributed denial of service attacks  
Several deterrence mechanisms suitable for content distribution networks (CDN) are provided. These include a hash-based request routing scheme and a site allocation scheme. The hash-based request...
7831800 Technique for prefetching data based on a stride pattern  
A processor system (100) includes a central processing unit (102) and a prefetch engine (110). The prefetch engine (110) is coupled to the central processing unit (102). The prefetch engine (110)...
7831799 Speculative address translation for processor using segmentation and optional paging  
An improved address translation method and mechanism for memory management in a computer system is disclosed. A segmentation mechanism employing segment registers maps virtual addresses into a...
7831936 Structure for a system for controlling access to addressable integrated circuits  
A design structure for a circuitry access system for controlling access to addressable circuit elements of an integrated circuit. The circuitry access system includes a first storage element...
7823161 Intelligent memory device with variable size task architecture  
A variable task size architecture is disclosed. A system partition is included that is dedicated to system use. The system partition contains a number of specifiers that describe the number of...
7822965 BIOS file switching method and controller device thereof  
A file switching method of a Basic Input/Output System (BIOS) file is disclosed. Upon a received read instruction, a timer for a predetermined timing is initiated, and a first data page having a...
7818475 Storage switch mirrored write sequence count management  
A storage switch is disclosed that facilitates mirroring of data. For example, a target is mirrored when an identical (or almost identical) copy of the data is stored in two or more separate...
7814294 Memory device, memory controller and memory system  
An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a...
7809924 System for generating effective address  
Method, system and computer program product for generating effective addresses in a data processing system. A method, in a data processing system, for generating an effective address includes...
7805589 Relative address generation  
Techniques to efficiently handle relative addressing are described. In one design, a processor includes an address generator and a storage unit. The address generator receives a relative address...
7793071 Method and system for reducing cache conflicts  
Disclosed is a system and method for storing a plurality of data packets in a plurality of memory buffers in a cache memory for reducing cache conflicts. The method includes determining size of...
7779227 Memory management apparatus and method for optical storage system  
A memory management apparatus and a related method thereof for accessing digital versatile disc(DVD) data stored in a memory device are disclosed. The memory management apparatus includes an...
7773589 Load-balancing, fault-tolerant storage system  
There is provided architecture of a storage system, which has high scalability, low performance ununiformity, and strong fault tolerance, and a control method thereof. The storage system is...
7769961 Systems and methods for sharing media in a computer network  
A computerized method for sharing removable storage media in a network, the method comprising associating, in an index entry, a first piece of removable storage media in a first storage device...
7769913 Method and apparatus for assigning a local identifier to a cluster interconnect port in a network storage system  
A network storage system includes a non-volatile memory to store data including a log of received data access requests, and a cluster interconnect adapter through which to send data to a cluster...
7739467 Semiconductor memory and data access method  
While a semiconductor memory operates in a first operation mode with high security, an encrypted command is inputted and then decoded to acquire the first address information. After the...
7734893 Method for speeding up page table address update on virtual machine  
A method is provided which eliminates redundancy from the shadow PT operation performed by the virtual machine monitor (VMM) when the guest operating system running on a virtual machine updates a...
7725681 Parallel processing array  
A processing element (1) forming part of a parallel processing array such as SIMD comprises an arithmetic logic unit (ALU) (3), a multiplexer (MUX) (5), an accumulator (ACCU) (7) and a flag...
7725677 Method and apparatus for improving segmented memory addressing  
A method and apparatus for breaking complex X86 segment operations and segmented memory addressing into explicit sub-operations so that they may be exposed to compiler or translator-based...
7721011 Method and apparatus for reordering memory accesses to reduce power consumption in computer systems  
A reordering command queue for reordering memory accesses in a computer system. The reordering command queue may reduce the power that is typically used up in computer systems when performing...
7715995 Design structure for measurement of power consumption within an integrated circuit  
An design structure for measuring power consumed during operation of an integrated circuit. The design structure including: a data processing circuit having an input and an output, the data...
7711924 Managing volumes in volume groups  
Provided are a method, system, and program for managing volumes in volume groups configured in a storage system. A first set of volumes is assigned to a first volume group and a first host is...
7707385 Methods and apparatus for address translation from an external device to a memory of a processor  
Methods and apparatus provide for adding a base address to an external address to produce first intermediate address; using only a first portion of the first intermediate address as a pointer to...
7707351 Methods and systems for an identifier-based memory section  
A storage system that may include one or more memory devices, a memory interface device corresponding to one or more of the memory devices, which are organized in sections, and a section...
7702883 Variable-width memory  
A variable-width memory may comprise multiple memory banks from which data may be selectively read in such a way that overall memory access requirements may be reduced, which may result in...
7702882 Apparatus and method for performing high-speed lookups in a routing table  
A lookup circuit for translating received addresses into destination addresses. The lookup circuit comprises M pipelined memory circuits for storing a trie table for translating a first received...
7685406 Determination of current stack pointer value using architectural and speculative stack pointer delta values  
A technique for reducing stack pointer adjustment operations when stack dependent operations, which correspond to stack dependent instructions, are encountered includes setting a stack pointer to...
7669034 System and method for memory array access with fast address decoder  
A method and data processing system for accessing an entry in a memory array is provided using base and offset addresses without adding the base and offset addresses. PGZO encoding is performed on...
7664939 Method and apparatus for detecting false operation of computer  
A program to be executed by a computer is divided into a plurality of code blocks, and, a unique code block ID is allotted to each code block. At the moment when the execution of the program is...
7664929 Data processing apparatus with parallel operating functional units  
A program of instruction words is executed with a VLIW data processing apparatus. The apparatus comprises a plurality of functional units capable of executing a plurality of instructions from each...
7650440 Peripheral supplied addressing in a simple DMA module  
A method of performing a direct memory access has the steps of selecting a peripheral device for performing a direct memory access through a direct memory access controller; providing a partial...
7643549 Wireless device having a hardware accelerator to support equalization processing  
The present invention provides an equalizer processing module within a wireless terminal having an equalizer interface that receives an incoming baseband signal from a baseband processor operably...
7634636 Device, system and method of reduced-power memory address generation  
Devices, systems and methods of reduced-power memory address generation. For example, an apparatus includes: a carry save adder including at least a first set of adders and a second set of adders,...
7634635 Systems and methods for reordering processor instructions  
Systems and methods for reordering processor instructions. In accordance with a first embodiment of the present invention, a microprocessor comprises circuitry to process an instruction extension,...
7617382 Method and apparatus for decompressing relative addresses  
A method and apparatus for decompressing relative addresses. A compressed relative address is retrieved from one or more micro-operation entries of a micro-operation storage and an uncompressed...