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8386747 Processor and method for dynamic and selective alteration of address translation  
Non-intrusive techniques have been developed to dynamically and selectively alter address translations performed by, or for, a processor. For example, in some embodiments, a memory management unit...
8381023 Memory system and computer system  
A memory system according to the present invention includes, in addition to an computing device, a plurality of first blocks that are provided to store information including user information, and...
8359455 System and method for generating real addresses using a connection ID designating a buffer and an access pattern  
A system and method for generating a real address in data memory in response to a read/write request may include generating an access request to at least one of read and write data to the data...
8352709 Direct memory access techniques that include caching segmentation data  
A memory access technique, in accordance with one embodiment of the present invention, includes caching segmentation data. The technique utilizes a separate memory for storing a plurality of...
8341359 Systems and methods for sharing media and path management in a computer network  
A method of dynamically sharing a media volume in a network includes associating a first media management module with a first media volume of a first storage device, associating a second media...
8332622 Branching to target address by adding value selected from programmable offset table to base address specified in branch instruction  
Methods and systems consistent with the present invention provide a programmable table which allows software to define a plurality of branching functions, each of which maps a vector of condition...
8319774 Constant buffering for a computational core of a programmable graphics processing unit  
Embodiments of the present disclosure are directed to graphics processing systems, comprising: a plurality of execution units, wherein one of the execution units is configurable to process a...
8316214 Data access tracing with compressed address output  
A moving window history of at least one previous data address accessed by a processor is maintained, the at least one previous data address in the history each being associated with an index. A...
8289971 Data transmission method  
A method of transmitting data between a plurality of inter-connected elements. The method comprises receiving a message from a first element, said message comprising a routing key plus optionally...
8285971 Block driven computation with an address generation accelerator  
A processor includes at least one execution unit that executes instructions, at least one register file, coupled to the at least one execution unit, that buffers operands for access by the at...
8285972 Lookup table addressing system and method  
Lookup table addressing of a set of lookup tables in an external memory is achieved by: transferring a data word from a compute unit to an input register in a data address generator; providing in...
8281106 Specifying an addressing relationship in an operand data structure  
A processor includes at least one execution unit that executes instructions, at least one register file, coupled to the at least one execution unit, that buffers operands for access by the at...
8266373 Content addressable memory (CAM) device and method for updating data by multiplexing between key register and mask value input  
A content addressable memory (CAM) can include a CAM memory array having both a data field and a mask field. A multiplexer (MUX) can selectively load data from either a register or an external...
8259339 Image forming apparatus  
An image forming apparatus includes a memory that stores therein a control program, a central processing unit that executes the control program stored in the memory, a print engine controlled by...
8254204 Burst address generator and test apparatus including the same  
A burst address generator includes a burst bit counter for receiving at least one burst bit, and increasing or decreasing the at least one burst bit, a burst bit splitter for receiving the...
8255593 Direct memory access with striding across memory  
A DMA device may include an offset determination unit configured to determine a first offset for a DMA transfer and a data transfer unit. The data transfer unit may be configured to receive a...
8195919 Handling multi-cycle integer operations for a multi-threaded processor  
Determining an effective address of a memory with a three-operand add operation in single execution cycle of a multithreaded processor that can access both segmented memory and non-segmented...
8185895 Method, apparatus and program storage device for providing an anchor pointer in an operating system context structure for improving the efficiency of accessing thread specific data  
A method, apparatus and program storage device for providing an anchor pointer in an operating system context structure for improving the efficiency of accessing thread specific data is provided....
8166251 Data prefetcher that adjusts prefetch stream length based on confidence  
In an embodiment, a processor includes a data cache and a prefetch unit coupled to the data cache. The prefetch unit is configured to identify a prefetch stream in cache misses from the data...
8140769 Data prefetcher  
In an embodiment, a processor includes a data cache and a prefetch unit coupled to the data cache. The prefetch unit is configured to detect one or more prefetch streams corresponding to load...
8127110 Method, system, and medium for providing interprocessor data communication  
A method of transmitting data between processors, including: establishing and storing an encoding method for each area of virtual address space of a first processor in a predetermined storage...
8127096 High capacity thin provisioned storage server with advanced snapshot mechanism  
Technologies for high capacity storage servers with thin provisioning can support an increased storage capacity and an increased number of snapshots within a data storage system while maintaining...
8120608 Constant buffering for a computational core of a programmable graphics processing unit  
Embodiments of systems and methods for managing a constant buffer with rendering context specific data in multithreaded parallel computational GPU core are disclosed. Briefly described, one method...
8108651 Programmable signal processing circuit and method of interleaving  
A programmable signal processing circuit is used to (de-)interleave a data stream. Data from the signal stream is stored in a data memory (28) and read in a different sequence. The programmable...
8095767 Arbitrary precision floating number processing  
Techniques for providing arbitrary precision floating number (APFN) processing are disclosed. In some aspects, an APFN store may be used to store a large number (i.e., an APFN) having many...
8095769 Method for address comparison and a device having address comparison capabilities  
A method for address comparison, the method includes: (i) receiving an input address; (ii) determining whether the input address is within a memory segment out of a group of memory segments by...
8086823 Method for speeding up page table address update on virtual machine  
A method is provided which eliminates redundancy from the shadow PT operation performed by the virtual machine monitor (VMM) when the guest operating system running on a virtual machine updates a...
8078828 Memory mapped register file  
A method and apparatus for operating a memory mapped register file. The method includes: receiving a source index input having a length of T−1 bits, the source index input identifying one of a...
8074027 Multi-level read caching for multiplexed transactional logging  
A transactional logging service is provided to user-mode and kernel-mode log clients by utilizing a marshalling area to buffer a set of log records that a log client assembles into a log stream....
8037440 Optimization of ROM structure by splitting  
A method for designing a read-only memory (ROM), and related device, includes partitioning a dataset into two or more sub-datasets that each have the same address space, but are of a smaller...
8032718 Systems and methods for sharing media in a computer network  
A computerized method for sharing removable storage media in a network, the method comprising associating, in an index entry, a first piece of removable storage media in a first storage device...
8026921 Driving method, driving circuit and driving apparatus for a display system  
A table-based driving circuit for displays that switches between a normal operational mode and a read table block mode. The driving circuit comprises an address sequencer and a memory. The memory...
8028148 Safe and efficient allocation of memory  
Aspects of the present invention are directed at centrally managing the allocation of memory to executable images in a way that inhibits malware from identifying the location of the executable...
8019969 Self prefetching L3/L4 cache mechanism  
Embodiments of the invention provide a look-aside-look-aside buffer (LLB) configured to retain a portion of the real addresses in a translation look-aside (TLB) buffer to allow prefetching of data...
8019964 Dynamic address translation with DAT protection  
What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of any one of a region first table, a...
8019968 3-dimensional L2/L3 cache array to hide translation (TLB) delays  
Embodiments of the invention provide a look-aside-look-aside buffer (LLB) configured to retain a portion of the real addresses in a translation look-aside (TLB) buffer to allow prefetching of data...
8015389 Memory device, memory controller and memory system  
An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a...
8006066 Method and circuit configuration for transmitting data between a processor and a hardware arithmetic-logic unit  
A method for transmitting data of a plurality of data types between a digital processor and a hardware arithmetic-logic unit with at least one associated table memory, first involves preselecting...
8006065 Method and system for combining page buffer list entries to optimize caching of translated addresses  
Certain aspects of a method and system for combining page buffer list entries (PBLEs) to optimize caching of translated addresses are disclosed. Aspects of a method may include encoding at least...
7996646 Efficient encoding for detecting load dependency on store with misalignment  
In one embodiment, an apparatus comprises a queue comprising a plurality of entries and a control unit coupled to the queue. The control unit is configured to allocate a first queue entry to a...
7996561 ZigBee network device for separately determining network parameter and assigning addresses, and address assignment method thereof  
A ZigBee network device assigns addresses to its child devices. The ZigBee network device includes a communication section that connects the ZigBee network device to other devices and which...
7996651 Enhanced microprocessor or microcontroller  
An n-bit microprocessor device has an n-bit central processing unit (CPU); a plurality of special function registers and general purpose registers which are memory-mapped to a plurality of banks,...
7996620 High performance pseudo dynamic 36 bit compare  
A cache memory high performance pseudo dynamic address compare path divides the address into two or more address segments. Each segment is separately compared in a comparator comprised of static...
7987322 Snoop request management in a data processing system  
Snoop requests are managed in a data processing system having a cache coupled to a processor that provides access addresses to the cache. Snoop queue circuitry provides snoop addresses to the...
7975125 Method for read-only memory devices  
A ROM comprises several bit output lines and X address decode lines, and stores a data set. Each address decode line stores a unique data word. Addresses in the data set that have the same data...
7966474 System, method and computer program product for translating storage elements  
A system, method and computer program product for translations in a computer system. The system includes a general purpose register containing a base address of an address translation table. The...
7953955 Methods and apparatus for automated generation of abbreviated instruction set and configurable processor architecture  
A systematic approach to architecture and design of the instruction fetch mechanisms and instruction set architectures in embedded processors is described. This systematic approach allows a...
7949852 Memory system, computer system and memory  
The correspondence between logical addresses and physical addresses is determined so that the logical addresses in ascending order may be assigned to the physical addresses in ascending order with...
7941595 Methods and systems for a memory section  
A storage system that may include one or more memory devices, a memory interface device corresponding to one or more of the memory devices, which are organized in sections, and a section...
7929830 Recording, reproducing, and recording/reproducing apparatuses for recording input data in a recording medium capable of non-linear access and methods thereof  
In recording, reproducing, and recording/reproducing apparatuses and methods thereof, while endlessly-recording first data, desired second data can be easily stored. The present invention...