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5600813 Method of and circuit for generating zigzag addresses  
In order to generate zigzag addresses for Discrete Cosine Transformation DCT data arranged in the form of a square matrix, row differentials (Δy) and column differentials (Δx) being differentials...
5590302 Device for generating structured addresses  
A device for generating structured addresses indicating an address position in a memory to be accessed. This device comprises first and second structured address generating devices and receives...
5586279 Data processing system and method for testing a data processor having a cache memory  
A cached processor (2) comprises a cache memory (8') having mode switching means for selecting an address capture mode whereby information, such as data and/or instructions, can be captured and...
5579500 Control apparatus for controlling data read accesses to memory and subsequent address generation scheme based on data/memory width determination and address validation  
An apparatus and method for controlling data read access to memory, in response to an access request sent through a system bus. The apparatus includes an data storage device for preserving data...
5577219 Method and apparatus for preforming memory segment limit violation checks  
A method and apparatus for determining if an effective address for a memory access in a computer processor is above an expand-down memory segment. The apparatus comprises a memory segment limit...
5564059 Simplified protocol for expanding a fixed width bus in an industrial controller  
The present invention provides an efficient method of transferring multi-word data across a fixed width parallel bus normally transmitting a single word at a time by allocating part of the bus...
5564030 Circuit and method for detecting segment limit errors for code fetches  
A segment limit check circuit performs limit checks on fetch addresses generated by a CPU. The circuit and method for performing the fetch limit check are simplified over the prior art by...
5553260 Apparatus for expanding compressed binary data  
A data expansion apparatus that performs data expansion operation for a data block unit in a constant period of time is provided. First and second memory devices are first initialized by storing...
5553258 Method and apparatus for forming an exchange address for a system with different size caches  
The present invention is directed to a method and apparatus for performing exchange transactions between caches and a main memory of a computer system, the caches and main memory being coupled to...
5535173 Data-storage device  
To resolve problems associated with the use of an AUDIO type memory with defective cells without concern for groups of defective cells in such memories, the sounds to be recorded are stored at...
5535353 Address generating circuit for data compression  
An address generating circuit for data compression includes an X-address generating circuit (10), a Y-address generating circuit (20), an XY-address generation control circuit (30) and a defect...
5524228 Memory control circuit for reducing the number of row address signals  
A method of accessing a dynamic random access memory, including the steps of latching an upper address of the most recent address signal supplied from a requesting element, sending out the upper...
5524223 Instruction accelerator for processing loop instructions with address generator using multiple stored increment values  
An instruction accelerator which includes an instruction source, and a single instruction multiple data array processor which executes the instructions supplied by the instruction source. A loop...
5524229 Address generating circuit and CD-ROM device using the same  
An address generating circuit for accessing a RAM for a CD-ROM device includes line and column counters for counting lines and columns of addresses in the RAM. The address generating circuit also...
5517633 System for controlling an internally-installed cache memory  
A cache uses A bits of an offset portion which are not subjected to the address translation of the logical address and B bits of the portion other than the offset portion, which are subjected to...
5493662 Apparatus for enabling exchange of data of different lengths between memories of at least two computer systems  
In an apparatus for use in a computer system for accessing to a main memory when a desired datum is not memorized in a cache memory, a supplementary memory is included in the apparatus for...
5490264 Generally-diagonal mapping of address space for row/column organizer memories  
A method for storing data in a generally-diagonal pattern in blocks of a flash EEPROM array by which the least number of memory cells are affected by a failure of either a row conductor or a...
5483643 Control circuit for data transfer between a main memory and a register file  
A control circuit for data transfer between a main memory and a register file. Firstly, the control circuit acquires, via a selector, a save area mask (SAM) data from external circuitry. A...
5481687 Method for reducing the number of bits in a binary word representing a series of addresses  
A method for reducing the number of bits in a binary word (AI) which represent a series of addresses, called initial addresses, having a first step (E1) which successively extracts from each...
5479632 Microcomputer having two-level memory to facilitate calculation of effective addresses  
A microcomputer includes a layered memory having a higher layer for storing a series of instructions forming a program to be executed by the microcomputer and a lower layer, having an upside layer...
5479626 Signal processor contexts with elemental and reserved group addressing  
The signal processor including a CPU 10 which selects a context register 16, the contents of which configure an address generator 20 and a data type converter 22. A narrow parameter from the CPU...
5465337 Method and apparatus for a memory management unit supporting multiple page sizes  
A memory management unit for translating a virtual address into a corresponding physical address including a translation lookaside buffer and a comparator. The translation lookaside buffer...
5440705 Address modulo adjust unit for a memory management unit for monolithic digital signal processor  
A memory management unit suitable fo use in a digital signal processor having internal and eternal memories is described. The unit is especially designed to facilitate numeric algorithms such as...
5408626 One clock address pipelining in segmentation unit  
A microprocessor which comprises a three input adder, a two input adder, apparatus for providing the components of a virtual address to the first and second adders on a first clock period, and...
5408673 Circuit for continuous processing of video signals in a synchronous vector processor and method of operating same  
A data processing apparatus includes a dual port data input register, first and second sequential ring counters, first and second register files, first and second data transfer circuits, a dual...
5396607 Matrix address generator and multivalue gradation processor having the same  
The present invention provides a matrix address generator for generating horizontal and vertical addresses in various patterns in the case where a memory table matrix provided in gradation data...
5388239 Operand address modification system  
A system of adding an operand address included in an instruction word to the contents of a modification register to obtain an effective address, wherein address data which designates each of a...
5388234 Finite state automation text search apparatus having two-level memory structure  
A finite state automaton (FSA) text search apparatus converts each of successively received binary code numbers, representing successive characters of a text to be searched, into two portions. Two...
5386523 Addressing scheme for accessing a portion of a large memory space  
A method for generating an address for addressable locations of a computer system where two registers are overlapped. Those bits of the two registers that overlap are logically combined together...
5386534 Data processing system for generating symmetrical range of addresses of instructing-address-value with the use of inverting sign value  
A data processing system (10) performs indexed addressing, autoincrementing, and autodecrementing using power of two byte boundaries. For example, a 5-bit offset allows a user to progress sixteen...
5357620 Bit addressing system  
A bit addressing system is disclosed in which on N-bit long addressing for the main storage is executed by means of a computation including a plurality of fields in an addressing operand. When...
5355462 Processor data memory address generator  
A processor data memory address generator is adapted to receive a control word from a program controller receiving instructions from a program memory addressed by an instruction counter and...
5339402 System for connecting an IC memory card to a central processing unit of a computer  
An address storing device is provided for storing segment addresses based on data applied from a CPU. An IC memory card set in a computer is addressed with a low-order 8 bits address applied from...
5337416 Apparatus for managing page zero accesses in a multi-processor data processing system  
Apparatus for use in a multi-CPU data processing system (10) wherein each CPU (12-18) is coupled to a common bus (20) and through the common bus to a main memory (28). The apparatus provides a...
5335333 Guess mechanism for faster address calculation in a pipelined microprocessor  
A processor in which instructions and data at logical addresses are mapped onto real memory locations at physical addresses that are translated from the logical addresses by a translation...
5321824 Accessing last recorded data in a continuation chain  
A write-once read-many (WORM) disk stores data in continuation chains. Each chain being arranged as a plurality of groups of contiguous datastoring areas (such as disk sectors, clusters of...
5303389 Data processing system for processing units having different throughputs  
In a data processing system including at least two processing units having different throughputs for performing sequential access upon a main storage unit, the number of elements of the main...
5293596 Multidimensional address generator and a system for controlling the generator  
A multidimensional address generator for generating one-dimensional addresses respectively corresponding to P1 ×P2 × . . . ×PN data of a predetermined region of an N-dimensional entire data array...
5293594 Data processing system having a plurality of register groups and a logical or circuit for addressing one register of one of the register groups  
In order to divide a memory addressed unidimensionally into a plurality of memory areas and to manage efficiently these memory areas, the address to be accessed inside the memory is determined on...
5282275 Address processor for a signal processor  
The invention relates to an address processor for a signal processor. This address processor comprises means for address calculation in a read/write memory containing at least one circular buffer...
5280595 State machine for executing commands within a minimum number of cycles by accomodating unforseen time dependency according to status signals received from different functional sections  
A virtual memory unit (VMU) includes a state machine for controlling its operations in response to commands received from another unit. The state machine includes a plurality of programmable array...
5218684 Memory configuration system  
A system permitting configuring of its total memory space includes a processor, an external operating device having a first address space and a bus coupling said central processing unit and the...
5210840 Address space control apparatus for virtual memory systems  
In a disclosed embodiment of the address space control apparatus, each general-purpose register usable as a base register is associated with another general-purpose register in addition to an...
5210839 Method and apparatus for providing a memory address from a computer instruction using a mask register  
A method and apparatus are provided for enabling a computer that is capable of running programs utilizing different address sizes to run those programs without having to modify the computer's...
5201040 Multiprocessor system having subsystems which are loosely coupled through a random access storage and which each include a tightly coupled multiprocessor  
A data processing system which has a plurality of sets of sub-systems, with each set including: a plurality of processors; a main storage; and a controller for controlling the transfer between at...
5197140 Sliced addressing multi-processor and method of operation  
A multi-processor system arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several...
5193161 Computer system having mode independent addressing  
A computer system and method for operating a computer system capable of running in mutually incompatible real and protected addressing modes, in which programs written for one mode can be run in...
5185874 Address generator for high speed data averager  
An address generator that provides equivalent time sampling for a time domain reflectometer generates read and write addesses for simultaneous application to an aquisition memory over an address...
5165039 Register file for bit slice processor with simultaneous accessing of plural memory array cells  
A register file for a bit slice ALU includes a static RAM array (86) which is addressable by two input read addresses. The addresses decoded by decoders (104) and (106) for input to the array...
5150471 Method and apparatus for offset register address accessing  
In a pipeline data processing system, a method for additively converting an address expressed in offset form to a corresponding real address in main memory (assuming that such address exists in...