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5784713 Address calculation logic including limit checking using carry out to flag limit violation  
Address calculation logic in which an adder carry out flags a segment limit violation is used, in an exemplary embodiment, in a 486 type microprocessor. An effective address adder (24) and a three...
5784710 Process and apparatus for address extension  
Circuitry within a system memory controller of a data processing system enables an M-bit processor to address a memory location that requires an N-bit address, wherein N is greater than M. Thus, a...
5765220 Apparatus and method to reduce instruction address storage in a super-scaler processor  
A system for storing addresses of instructions being executed in a processor by storing an address of a first instruction in a line of cache or memory in an instruction address queue. With each...
5764939 RISC processor having coprocessor for executing circular mask instruction  
An add with circular mask operation is executed in a RISC processor which includes a coprocessor having a register for storing a circular mask value. A circular mask instruction to the coprocessor...
5765219 Apparatus and method for incrementally accessing a system memory  
Data storage apparatus comprises: a memory having a plurality of addressable memory locations for storage of data items and memory address input means for receiving addresses of locations to be...
5765215 Method and system for efficient rename buffer deallocation within a processor  
A method and system are disclosed for managing the deallocation of a rename buffer allocated to an update instruction within a processor. The processor has a number of rename buffers for...
5765181 System and method of addressing distributed memory within a massively parallel processing system  
A system and address method for extracting a PE number and offset from an array index. According to one aspect of the present invention, a processing element number is assigned to each processing...
5765218 Address generating circuit for generating addresses separated by a prescribed step value in circular addressing  
An address generating circuit of simple configuration for circular addressing. A bit isolating circuit 304 extracts an index from an input address. When a step value input to an adder 302 is...
5765221 Method and system of addressing which minimize memory utilized to store logical addresses by storing high order bits within a register  
An improved method of addressing within a pipelined processor having an address bit width of m+n bits is disclosed, which includes storing m high order bits corresponding to a first range of...
5761741 Technique for addressing a partial word and concurrently providing a substitution field  
A method and apparatus for addressing memory is disclosed. In one embodiment, a procedure for providing a word with fixed width, having a fixed number of bits to be used for addressing variable...
5761740 Method of and apparatus for rapidly loading addressing registers  
A method of and apparatus for rapidly modifying the user base registers of an instruction processor. In accordance with the present invention, a load base register user instruction may request an...
5752273 Apparatus and method for efficiently determining addresses for misaligned data stored in memory  
An apparatus and method for efficiently generating the consecutive addresses needed to access misaligned or doubleword length data stored in the memory of a general purpose microprocessor. The...
5751988 Microcomputer with memory bank configuration and register bank configuration  
A microcomputer includes a plurality of register banks and a plurality of memory bank select registers coupled to the respective register banks. A register bank select register temporarily stores...
RE35794 System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache  
A super-scaler processor is disclosed wherein branch-prediction information is provided within an instruction cache memory. Each instruction cache block stored in the instruction cache memory...
5749085 Electronic memory addressing device especially for a memory organized into banks  
A first and a second input ports, the sum of whose inputs is greater than an integer n, receive pairs of first words of k bits and of second words of n-k bits, each set of n bits representing an...
5742755 Error-handling circuit and method for memory address alignment double fault  
In an χ86-compatible processor capable of operating in a protected mode of operation in which privilege levels are assigned to tasks executing therein, an application task being assigned a lowest...
5740465 Array disk controller for grouping host commands into a single virtual host command  
A plurality of commands which may be sent sequentially from a host computer are interpreted by a host command interpreter to generate a disk command for each disk unit. When these commands make up...
5740457 Electronic dictionary, its production method, and index compression and decompression device  
An electronic dictionary comprises a dictionary medium; dictionary data composed of a plurality of dictionary data elements and stored in the dictionary medium; and an index file showing storage...
5724540 Memory system having a column address counter and a page address counter  
A memory system which includes a memory array having a column address input and a page address input, addressed by a column pointer and a page pointer; a processor for accessing the memory array...
5712999 Address generator employing selective merge of two independent addresses  
An address generator (120) forms a selective merge of two addresses. First (610) and second (620) address units generate respective first and second N bit address. Each unit (610, 620) preferrably...
5706461 Method and apparatus for implementing virtual memory having multiple selected page sizes  
A method and apparatus for implementing virtual memory having multiple selected page sizes are provided. A virtual address includes a map index and a frame offset. A selector mechanism receives...
5699545 Row address generator in a memory address system  
A system and method for generating row addresses for a memory structure on a column by column basis. In accordance with the novel method, a column read start address (SC) is subtracted from a...
5699544 Method and apparatus for using a fixed width word for addressing variable width data  
A method for addressing memory uses a word with a fixed width, having a fixed number of bits, and having a width defining field and address field. The procedure is adapted to addressing variable...
5696930 CAM accelerated buffer management  
A method and apparatus for managing effectively data and command buffers in an I/O subsystem utilizes a content addressable memory (CAM) array (36) having a plurality of CAM storage locations (SL1...
5694569 Method for protecting a volatile file using a single hash  
The disclosed methodology permits an insecure computing system to safely perform high security electronic financial transactions. The present invention permits the hash of a file to be taken on an...
5694568 Prefetch system applicable to complex memory access schemes  
A computer processor which speculatively issues prefetch addresses for indirect as well as linear memory traversals after entering an armed state. A particular embodiment of the invention includes...
5694438 Method and apparatus for managing a data symbol received in a time diversity communication system  
A method and apparatus (400) manages a current data symbol received by a receiver (122) in a frame of data of a time diversity communication system (102, 104). A symbol counter (402) counts a...
5684974 Method and apparatus for controlling reconfiguration of storage-device memory areas  
An apparatus and method for controlling the reconfiguration of the physical storage area in a real storage device employed by an information processing system.The invention includes an address...
5680568 Instruction format with sequentially performable operand address extension modification  
A data processor which has an operand instruction having an operation code specifying portion to specify the kind of operation and an effective address specifying field showing the effective...
5680598 Millicode extended memory addressing using operand access control register to control extended address concatenation  
A millicode instruction loads a millicode address extension register with extended address bits, and an operand access control register that signals when a logical address is to be extended by the...
5680567 Efficient addressing of large memories  
A computer memory device has a predetermined number of individually addressable storage cells and an internal addressing mechanism for storing a full address that determines which of the...
5666508 Four state two bit recoded alignment fault state circuit for microprocessor address misalignment fault generation  
An apparatus for controlling address alignment fault generation employing a recoded two bit structure. This alignment fault state circuit stores one of four states corresponding to whether the...
5666510 Data processing device having an expandable address space  
A CPU has an upper compatibility with a low-order CPU to expand a continuously usable address space relatively. For latching data information, registers are constructed for being an address...
5659698 Method and apparatus for generating a circular buffer address in integrated circuit that performs multiple communications tasks  
A circular buffer address generation unit (630) may be accomplished by first determining a potential next address (635) based on a current address (644) and an address offset value (646). Having...
5659580 Data interleaver for use with mobile communication systems and having a contiguous counter and an address twister  
The present invention includes a data buffer, a contiguous counter and an address twister. The contiguous counter generates a contiguous sequence of addresses which are used to load data into the...
5657466 Circuit for designating write and read address to provide a delay time in a sound system  
A write address and a read address are generated by use of a pointer register and a single register set common to the write and read addresses. The read register is obtained by an addition or...
5655132 Register file with multi-tasking support  
A register file connected to a data memory and an arithmetic logic unit for temporary storage of operands, and a method of managing such register file permits the register file to be used to...
5655139 Execution unit architecture to support X86 instruction set and X86 segmented addressing  
A microprocessor execution unit includes an arithmetic unit and an addressing unit. The arithmetic unit performs arithmetic and logical operations on operands. The addressing unit operates in...
5651126 Method and apparatus for reducing transitions on computer signal lines  
A method and apparatus for eliminating unnecessary address transitions on an DRAM address bus and DRAM write enable line. In a known DRAM controller and DRAM array, all address transitions on the...
5649144 Apparatus, systems and methods for improving data cache hit rates  
A processing system is provided which generates a memory address and presents the memory address to a cache to retrieve corresponding data when such corresponding data is encached therein. The...
5649142 Method and apparatus for translating addresses using mask and replacement value registers and for accessing a service routine in response to a page fault  
A method and apparatus for translating a first address in a first address space, such as a processor address space, to a second address in a second address space, such as system address space, and...
5649143 Apparatus and method for providing a cache indexing scheme less susceptible to cache collisions  
Logic circuitry and a corresponding method for computing an indexed set address utilized by a cache to mitigate the probability of a conflict miss occurring for a given memory access. Implemented...
5644749 Parallel computer and processor element utilizing less memory  
The present invention discloses processor elements interconnected via a network in a parallel computer. The processor element includes a memory unit for storing a program and, per array-variable...
5640528 Method and apparatus for translating addresses using mask and replacement value registers  
A method and apparatus for translating a first address in a first address space, such as a processor address space, to a second address in a second address space, such as a system address space,...
5623680 Finite state machine for process control  
A model of a finite state machine suited for implementation in a microcomputer includes logical specifications stored in memory which determine whether a change of outputs should be effected in...
5619715 Hardware implementation of string instructions  
A data processor processes data strings from memory where the data strings do not begin or end at a memory boundary. A string is defined in memory by a starting address, a byte count defining the...
5617560 System for handling platform independent optical card by separating during a read and recombining during a write generic directory information and OS dependent directory information  
The present invention is characterized in that in a system for accessing an optical card under the control of a general-purpose operating system (OS), the directory format of the optical card is...
5611065 Address prediction for relative-to-absolute addressing  
A base address prediction system for predicting one of a plurality of base addresses to be added to a known relative address in order to generate an absolute address. An actual base address...
5608888 Method and apparatus for mapping data of a 2-dimensional space from a linearly addressed memory system  
A 2-dimensional display space is mapped into the external DRAM addresses by embedding in the address space X and Y vectors of the display space. The mapping of the X and Y vectors allows a...
5600814 Data processing unit for transferring data between devices supporting different word length  
A data processing system comprising a main memory 10 with a 32-bit longword data bus 11 and an address bus 12, and a link unit 20 using 16-bit shortwords. The link unit has two shortword memories...