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5978895 Method for speeding mathematical operations in a processor core  
Method and apparatus are disclosed for increasing the speed of mathematical operations in a processor core. The invention increases the speed of mathematical operations by delivering a first...
5974520 Computer address translation system and method for converting effective or logical address to physical address  
A computer address translation method and system applicable in CPUs for translating an effective address and a selector address into a physical address under the control of an invalidity signal...
5974495 Using a back-off signal to bridge a first bus to a second bus  
A PCI-bus is added to a VESA local bus (VL-bus) computer system using a VL-bus/PCI-bus bridge. The VL-bus/PCI-bus bridge claims a VL-bus cycle by asserting LDEV# to the VL-bus/system-bus bridge....
5963977 Buffer management and system coordination method  
A method of coordinating access to a data buffer including a plurality of data blocks, using a buffer list with a plurality of entries corresponding to the data blocks. Each buffer list entry...
5961580 Apparatus and method for efficiently calculating a linear address in a microprocessor  
A linear address generation apparatus is provided which adds the segment base address to the displacement provided in the instruction while the instruction is being decoded. The linear and logical...
5958038 Computer processor with two addressable memories and two stream registers and method of data streaming of ALU operation  
A processor having a modified Harvard architecture having first and second memories, an address register file divided into first and second sets of registers, first and second stream registers,...
5946716 Sectored virtual memory management system and translation look-aside buffer (TLB) for the same  
A memory management system is described which divides each virtual page into two or more sectors. Each of these sectors can then be individually loaded into memory in order to reduce bandwidth...
5941974 Serial interface with register selection which uses clock counting, chip select pulsing, and no address bits  
A method and apparatus for providing serially shifted data to a plurality of registers (51 through 56) begins by providing an enable signal (14). A first time portion of the enable signal (14) is...
5943693 Algorithmic array mapping to decrease defect sensitivity of memory devices  
A method and apparatus for addressing a memory device are described. A first logical address is translated into a first physical address to access a first storage location at a first row and a...
5940868 Large memory allocation method and apparatus  
Computer method and apparatus for allocating and accessing large memory. Under a given operating system, the invention apparatus creates multiple processes, each having a corresponding virtual...
5940863 Apparatus for de-rotating and de-interleaving data including plural memory devices and plural modulo memory address generators  
An apparatus for re-rotating and deinterleaving data includes (i) a first memory for storing D elements of rotated and interleaved data in D storage locations, (ii) a first addresser for...
5940877 Cache address generation with and without carry-in  
A cache system provides for accessing set associative caches with no increase in critical path delay, for reducing the latency penalty for cache accesses, for reducing snoop busy time, and for...
5937435 System and method for skip-sector mapping in a data recording disk drive  
A data recording disk drive includes a system and method for mapping around skip sectors, both bad sectors and spare sectors. A received logical block address is converted to a corresponding...
5924128 Pseudo zero cycle address generator and fast memory access  
A method and apparatus estimate the memory address needed for a low level programming instruction in reduced instruction set computing systems. Taking advantage of a known computing environment...
5918253 Memory address generator  
An address generator has a designating value storing section for storing a designating value for designating each of register sections of an offset register into an address register. The address...
5918252 Apparatus and method for generating a modulo address  
A method and apparatus for generating a modulo address for accessing a circular buffer. The method and apparatus accept as inputs a length L of the circular buffer, a current address A of the...
5913231 Method and system for high speed memory address forwarding mechanism  
A system and method for high speed memory address forwarding is presented. A method according to the present invention for high speed memory address forwarding for a processing system, the...
5913229 Buffer memory controller storing and extracting data of varying bit lengths  
A buffer memory controller allows to sequentially store sampled data having variable bit length. That is, rather than assigning each sampled data to a single word of the memory, the sampled data...
5913050 Method and apparatus for providing address-size backward compatibility in a processor using segmented memory  
This invention overcomes the address size backward compatibility problem by first subtracting the segment base address from the linear destination address of a branch instruction to generate a...
5911152 Computer system and method for storing data in a buffer which crosses page boundaries utilizing beginning and ending buffer pointers  
A computer system and method for storing data in pages of memory according to a data structure which is stored within the memory and identifies the pages of data. The data structure includes a...
5909704 High speed address generator  
An address generator (10) adapted for use with a first address source (12) and a second address source (14). The inventive generator (10) includes a first circuit (18-36) for selectively applying...
5903918 Program counter age bits  
An apparatus and method of efficiently and dynamically generating the addresses associated with a set of instructions in a microprocessor pipeline is disclosed. Program counter age bits associated...
5903919 Method and apparatus for selecting a register bank  
Method and apparatus for selecting one of a plurality of banks of registers in a register file of a data processor. The register specifier fields of an instruction are logically combined with...
5900023 Method and apparatus for removing power-of-two restrictions on distributed addressing  
An efficient integer-division-by-an-constant method and apparatus. This integer-division-by-an-constant is useful in calculations which must be performed often and/or quickly, and where the...
5897665 Register addressing for register-register architectures used for microprocessors and microcontrollers  
A microprocessor or microcontroller architecture which utilizes a 64 byte-register file in a unique manner. The lowest 16 bytes of the register file can be accessed as 16 8-bit registers (R0-R15),...
5897668 Memory system for storing information data and state-of-radio-transmission data  
In a memory system capable of using a common address for reading out a combination of upper-digit data and lower-digit data, there are provided an upper-digit memory element 1 for exclusively...
5893932 Address path architecture  
A microprocessor system integrated on a chip having one or more address generation devices, at least one memory location, and at least one peripheral unit. The address path is divided into two...
5889983 Compare and exchange operation in a processing system  
A technique for providing a compare-and-exchange (CMPXCHG) instruction which may be implemented in an instruction set requiring a limited number of source and destination operands for each...
5890222 Method and system for addressing registers in a data processing unit in an indirect addressing mode  
In a data processing unit, an instruction is loaded. Such an instruction includes an operation code field for storing an operation code and at least one operand field, where the operand field...
5881302 Vector processing unit with reconfigurable data buffer  
A vector processing unit includes data buffers between a storage and a vector processor. Each of the data buffers is divided into four virtual buffers. Each virtual buffer can store 16 words of...
5873126 Memory array based data reorganizer  
Memory system for internally rearranging fields in database records. The memory is separated into modules, each module separately addressable. Each memory module is addressed by selectively...
5860155 Instruction decoding mechanism for reducing execution time by earlier detection and replacement of indirect addresses with direct addresses  
The mechanism includes a virtual address detecting circuit for detecting the virtual address of the instruction code. When a virtual address is detected, an indicating signal is generated, which...
5860154 Method and apparatus for calculating effective memory addresses  
A macro instruction is provided for a microprocessor which allows a programmer to specify a base value, index, scale factor and displacement value for calculating an effective address and...
5860151 Data cache fast address calculation system and method  
The data cache features an improved mechanism for accessing data from the data memory array of a data cache, by generating a predicted address and using it to access the data cache array in...
5860107 Processor and method for store gathering through merged store operations  
First and second store instructions that target one or more locations in a cache memory are identified. A determination is made whether the cache memory is busy. In response to a determination...
5845314 Data storage apparatus, data reading apparatus and data transmission apparatus  
A data transmission apparatus including a plurality of buffers for sequentially receiving individual data to be stored in a plurality of memories at every predetermine period and storing supplied...
5835925 Using external registers to extend memory reference capabilities of a microprocessor  
A system and method of accessing a memory location within a system having a processor and a plurality of memory locations separate from the processor. The system includes a plurality of external...
5835972 Method and apparatus for optimization of data writes  
An improved method for performing memory writes from a processor in a personal computer system is provided whereby single writes are combined into burst writes based on detection of suitable write...
5835971 Method and apparatus for generating addresses in parallel processing systems  
An apparatus for generating an address to increase efficiency in parallel processing in a multiprocessor system. A global address generating unit is provided within a vector unit of each of...
5835973 Instruction processing unit capable of efficiently accessing the entire address space of an external memory  
In an instruction processing unit, a first register group having at least one register whose bit width is enough for designating a desired address in the entire address space of a memory, and a...
5835966 Semiconductor memory device and memory access system using a four-state address signal  
The disclosed is an DRAM which is accessible in response to four-state address signal. A two-state address signal generator receives the four-state address signal respectively defined by four...
5832290 Apparatus, systems and method for improving memory bandwidth utilization in vector processing systems  
Vector register circuitry is provided which includes a vector register file comprising at least one vector register having a plurality of elements, the vector register file further having at least...
5829051 Apparatus and method for intelligent multiple-probe cache allocation  
An apparatus for allocating data to and retrieving data from a cache includes a memory subsystem coupled between a processor and a memory to provide quick access of memory data to the processor....
5826057 Method for managing virtual address space at improved space utilization efficiency  
A method for managing virtual address space in which programs designed for smaller virtual address spaces in the multiple virtual memory scheme can be collectively allocated to a single enlarged...
5822789 Video memory arrangement  
By providing a digital video memory arrangement with first and second address generating circuits, digital video signals can be written at a first location of a non-mechanical memory and (almost)...
5822788 Mechanism for prefetching targets of memory de-reference operations in a high-performance processor  
A computer system provides enhanced performance when executing irregular code that include pointer de-reference operations. A memory controller of the computer system first fetches a pointer value...
5809557 Memory array comprised of multiple FIFO devices  
A multiple FIFO array which does not use numerous single FIFO devices is provided. The multiple FIFO array includes a memory partitioned into a plurality of N sections, each section corresponding...
5809534 Performing a write cycle to memory in a multi-processor system  
In a method and system of performing a write cycle to a memory address in a multi-processor system, a first write cycle is initiated to the memory address, and a second write cycle is initiated to...
5787496 Digital signal processor having a partitioned memory with first and second address areas for receiving and storing data in sychronism with first and second sampling clocks  
A digital signal processor includes first and second counters which increment from each initial address value in first and second address areas synchronous with first and second sampling clock...
5787497 Direct memory access control device for a ring buffer  
A DMA control device for generating an address value to a ring buffer according to the present invention is provided with an address generation circuit for generating address signals to the ring...