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6157981 Real time invariant behavior cache  
A memory and memory architecture for use by a processor executing real time code and a system on a chip including the processor and memory containing the code. An effective address is maintained...
6154825 Method and apparatus for addressing a memory resource comprising memory devices having multiple configurations  
A method and apparatus for accessing a memory resource, such as an array of DRAM modules, is described. The methodology commences with the receipt of a memory address during a memory access cycle....
6154805 Realtime clock with page mode addressing  
A realtime clock integrated circuit includes a memory (30) that has a plurality of addressable locations therein. The memory (30) has two portions, a lower portion and an upper portion. The lower...
6154827 Data processor capable of high speed accessing  
A data processor capable of accessing data with the data processing capacity of a central processing unit (CPU), even if the data processing capacity of the CPU within the data processor is larger...
6141742 Method for reducing number of bits used in storage of instruction address pointer values  
Variable-length instructions are prepared for simultaneous decoding and execution of a plurality of instructions in parallel by reading multiple variable-length instructions from an instruction...
6138212 Apparatus and method for generating a stride used to derive a prefetch address  
A central processing unit (CPU) of a computer has a data caching unit which includes a novel dual-ported prefetch cache configured in parallel with a conventional single-ported data cache. If a...
6131108 Apparatus, and associated method, for generating multi-bit length sequences  
Apparatus, and an associated method, for generating multi-bit sequences used, for instance, to form an address pointer or a data pointer of a computer system. The circuitry is embodied in a...
6128718 Apparatus and method for a base address register on a computer peripheral device supporting configuration and testing of address space size  
A method for providing a base address register in a computer system that allows the length of the base address portion of an address to be changed and thereby allows various sizes of address...
6125437 Virtual linear frame buffer addressing method and apparatus  
A virtual linear frame buffer addressing method and apparatus efficiently convert a linear address supplied by an application programming (API) into an X, Y address used in a rectangular memory...
6125435 Alignment of cluster address to block addresses within a semiconductor non-volatile mass storage memory  
A digital system is disclosed for use with a host, the digital system including a controller and a nonvolatile memory unit having memory locations organized in blocks with each block having a...
6119213 Method for addressing data having variable data width using a fixed number of bits for address and width defining fields  
In a method and apparatus for addressing memory there is a procedure for providing a word with fixed width, having a fixed number of bits to be used for addressing variable width data, and having...
6119198 Recursive address centrifuge for distributed memory massively parallel processing systems  
A method for extracting a PE number and offset from an array index by recursive centrifuging. According to one aspect of the present invention, a processing element number is assigned to each...
6115801 Device and method for increasing the internal address of a memory device using multifunctional terminals  
A semiconductor integrated, storage circuit device having at least a first enable terminal for enabling the device, and a first number of address terminals for inputting an external address formed...
6108803 Memory cell circuit for executing specific tests on memory cells that have been designated by address data  
A memory circuit, provided with address signal generating arrangement that includes first counter 72 for outputting first output data Q1 sequentially designating address signals for memory cells...
6108761 Method of and apparatus for saving time performing certain transfer instructions  
A method and apparatus for reducing processor response time to selected transfer instructions in an multi-instruction processor. The response time is shortened by using a fast path to generate...
6105120 Method for implementing multiple format addressing in an embedded microcontroller, a compiler being arranged for implementing the method, and a microcontroller being arranged for using the method and compiler  
Multiple format addressing is implemented in a microcontroller that has both ROM and RAM memory facility, processing facility, and bus facility for interconnecting the memory and processing...
6105126 Address bit decoding for same adder circuitry for RXE instruction format with same XBD location as RX format and dis-jointed extended operation code  
A computer processor floating point processor six cycle pipeline system where instruction text is fetched prior to the first cycle and decoded during the first cycle for the fetched particular...
6098160 Data pointer for outputting indirect addressing mode addresses within a single cycle and method therefor  
A data pointer for generating an indirect addressing mode address within a single cycle for a selected one of a plurality of multiple indirect addressing modes. The data pointer is used with a...
6098161 Method of generating address of coefficient memory in OFDM adaptive channel equalizer and apparatus employing the same  
A method and an apparatus for generating address of a coefficient memory in an OFDM adaptive channel equalizer are disclosed. The address generating apparatus comprises a signal generator for...
6094713 Method and apparatus for detecting address range overlaps  
A method and apparatus for detecting address range overlaps. According to one embodiment, a first mask is generated for a first address range and a second mask is generated for a second address...
6088763 Method and apparatus for translating an effective address to a real address within a cache memory  
A method and apparatus for translating an effective address to a real address within a cache memory are disclosed. As disclosed, a content-addressable memory contains a multiple of addresses, and...
6088781 Stride instruction for fetching data separated by a stride amount  
A microprocessor is configured to execute a stride instruction. In response to the stride instruction, the microprocessor performs a series of load memory operations. The address corresponding to...
6085302 Microprocessor having address generation units for efficient generation of memory operation addresses  
A microprocessor including address generation units configured to perform address generation for memory operations is provided. A reservation station associated with one of the address generation...
6081853 Method for transferring burst data in a microprocessor  
A method for burst transferring of data in a processing system is provided. The processing system has a data bus width of W bytes (W even) and a cache line length of L bytes (L even). The cache...
6081881 Method of and apparatus for speeding up the execution of normal extended mode transfer instructions  
A method and apparatus for reducing processor response time to selected transfer instructions in an instruction processor using a plurality of memory banks including four banks in a basic mode and...
6079005 Microprocessor including virtual address branch prediction and current page register to provide page portion of virtual and physical fetch address  
A microprocessor employs a branch prediction unit including a branch prediction storage which stores the index portion of branch target addresses and an instruction cache which is virtually...
6058464 Circuits, systems and method for address mapping  
An information processing system 400 includes a subsystem 402 having a processing resource 404 and a bus interface 403. An active logic mapping signal is presented to a mapping input bus interface...
6055652 Multiple segment register use with different operand size  
A new method and apparatus are used to check for segment limit violations during memory access. When a segment descriptor is retrieved during the initialization of a segment, the segment limit...
6052768 Circuit and method for modulo address generation with reduced circuit area  
The present invention relates to a modulo address generator and method thereof. The apparatus includes an adder which adds a current address value and an address increment value to generate an...
6049854 System and method for sharing physical memory among distinct computer environments  
Two or more operating systems to share a same physical memory while operating simultaneously within a hybrid computer system, without requiring modifications to the program code of the operating...
6049858 Modulo address generator with precomputed comparison and correction terms  
In accordance with the present invention, an address arithmetic unit provides a modulo addressing technique for addressing memory locations in a circular buffer. The address arithmetic unit...
6047365 Multiple entry wavetable address cache to reduce accesses over a PCI bus  
A method and apparatus for optimizing sample fetching in a peripheral component interconnect (PCI) environment. In one embodiment the present invention generates a first sample page base address...
6047364 True modulo addressing generator  
In accordance with the present invention, an address arithmetic unit provides a modulo addressing technique for addressing a circular buffer. The address arithmetic unit includes a first selector...
6044447 Method and apparatus for communicating translation command information in a multithreaded environment  
A method and apparatus are provided for communicating translation command information in a multithreaded environment in a computer system. The computer system includes a processor unit, an...
6044455 Central processing unit adapted for pipeline process  
A central processing unit includes an adder dedicated to address calculation provided separately from an ALU, a first address data route connected to a program counter and a stack pointer...
6038650 Method for the automatic address generation of modules within clusters comprised of a plurality of these modules  
A method of automatic address generation by units within clusters of a plurality of such units in which individual configurable elements of a unit can be addressed. It is thus possible to address...
6035384 Solid state disk drive address generator with multiplier circuit  
An address generator for a solid state disk drive device includes a hardware multiplier logic circuit dedicated to computation of the address by multiplying a block size by a logical block number,...
6032243 Data-transfer interconnection for signal and data transfer between CD-ROM decoder and buffer memory  
A data-transfer interconnection is devised for signal and data transfer between a CD-ROM decoder and a buffer memory associated with the CD-ROM decoder. In particular, the CD-ROM decoder including...
6032165 Method and system for converting multi-byte character strings between interchange codes within a computer system  
A method for converting a multi-byte dataword in a first extended interchange code to a multi-byte dataword in a second extended interchange code is disclosed. In accordance with the method and...
6029212 Method of handling arbitrary size message queues in which a message is written into an aligned block of external registers within a plurality of external registers  
A system and method of accessing a memory location within a system having a processor and a plurality of memory locations separate from the processor. The system includes a plurality of external...
6014733 Method and system for creating a perfect hash using an offset table  
A method and mechanism for converting a non-contiguous subset of values in a large range, such as selected Unicode code points, into a contiguous or mostly contiguous smaller range with a perfect...
6009504 Apparatus and method for storing data associated with multiple addresses in a storage element using a base address and a mask  
A method and apparatus for storing and retrieving data associated with multiple addresses in a storage element of a storage device having a number of storage elements, a first memory having a like...
6009493 Data transfer control method and apparatus for performing consecutive burst transfer operations with a simple structure  
A method and apparatus for controlling transfer of data in which a plurality of burst transfer operations starting from an arbitrary byte as a start address are performed consecutively without a...
6009503 Cache memory indexing using virtual, primary and secondary color indexes  
The memory device comprises a cache memory indexed by the cache index and group information of the virtual address. The physical address translated from the virtual address contains primary and...
6006314 Image processing system, storage device therefor and accessing method thereof  
A storage device has a relative address table. An address is sequentially generated by an address adder based on a start address and a plurality of relative addresses held in the relative address...
5991862 Modified indirect addressing for file system  
A logical address and a pointer entry for a file in an indirect address file system are translated into a physical address. A decision module tests a pointer flag in a present pointer entry. The...
5991863 Single carry/borrow propagate adder/decrementer for generating register stack addresses in a microprocessor  
A microprocessor (10) and system implementing the same is disclosed, in which stack-based register address calculation is performed in a single add cycle for instructions involving a PUSH...
5987584 Wavetable address cache to reduce accesses over a PCI bus  
A method and apparatus for optimizing sample fetching in a peripheral component interconnect (PCI) environment. In one embodiment the present invention generates a sample page base address...
5983333 High speed module address generator  
In accordance with the present invention, an address arithmetic unit provides a modulo addressing technique for addressing memory locations in a circular buffer. The address arithmetic unit...
5983309 Autonomous high speed address translation with defect management for hard disc drives  
An address translation unit is provided for logical to physical address conversion. In particular, apparatus and method are described for receiving a logical cylinder head sector for a logical...