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7596569 |
Method and program for space-efficient representation of objects in a garbage-collected system
A system includes a processor for executing a collector program to perform a method (e.g., a method of collection). The method includes using an object model during a collection phase that is...
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RE40904 |
Apparatus for generating target addresses within a circular buffer including a register for storing position and size of the circular buffer
The invention comprises a hardware constructed address generator for a circular buffer which can be of any size and be in any position in memory. The address generator calculates both an absolute...
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7579683 |
Memory interface optimized for stacked configurations
A semiconductor die includes a plurality of interconnection pads for connecting with a memory die. The two dies are packaged together in a stacked manner. The plurality of pads are disposed so that...
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7577818 |
Microprocessor program addressing arrangement having multiple independent complete address generators
An address-generating arrangement for a microprocessor has, in addition to its base address-generating unit, one or more address-generating expansion units, connected to the basic unity by an...
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7571299 |
Methods and arrangements for inserting values in hash tables
Methods and arrangements to insert values in hash tables are contemplated. Embodiments include transformations, code, state machines or other logic to insert values in a hash table stored in...
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7549037 |
Efficient off-host backup of a file set clone
A method, system, computer system, and computer-readable medium that enable a secondary host that is not the file system host to create a backup of a clone file set that shares at least one data...
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7509478 |
Program memory space expansion for particular processor instructions
A system efficiently expands program memory without extensively modifying the remaining microcontroller architecture. An address bus of N+M bits addresses 2 N memory locations in a regular portion...
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7506133 |
Method and apparatus for high speed addressing of a memory space from a relatively small address space
A method and apparatus for high speed addressing of a memory space from a relatively small address space. An N-bit bus interfaces with a memory device having a 2 M address memory space, where M is...
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7502909 |
Memory address generation with non-harmonic indexing
A method for generating a sequence of memory addresses for a multi-dimensional data structure and an address generation unit are disclosed. The address generation unit includes an ADDRESS register,...
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7475221 |
Circular buffer addressing
Methods and apparatus are provided for performing circular buffer addressing. Upper boundaries, lower boundaries, circular buffer lengths, addresses, and offsets are set to allow circular buffer...
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7466623 |
Pseudo SRAM capable of operating in continuous burst mode and method of controlling burst mode operation thereof
A pseudo SRAM which can perform read and write operations of data in a continuous burst mode in such a manner that it continuously generates burst row and column address signals, which gradually...
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7463585 |
System, method, and apparatus for load-balancing to a plurality of ports
A system, method, and apparatus for load balancing to a plurality of ports is presented herein. A miniport driver is adapted to multiplex and demultiplex traffic workload across the ports. The...
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7457937 |
Method and system for implementing low overhead memory access in transpose operations
Embodiments of the present invention recite a method and system for accessing data. In one embodiment of the present invention, a plurality of instances of data are stored in a memory device which...
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7454589 |
Data buffer circuit, interface circuit and control method therefor
There are provided a buffer circuit buffers data between a synchronous circuit and an asynchronous circuit, and a control method therefor. There are also provided an interface circuit that controls...
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7454557 |
System and method for booting from a non-volatile application and file storage device
A system for booting a microprocessor controlled system wherein a basic interface between the processor and peripheral devices is stored and retrieved from the general purpose application and file...
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7453761 |
Method and system for low cost line buffer system design
Various aspects of the low cost line buffer system allow a reduction in circuitry versus conventional approaches to line buffer design. A plurality of line buffers such that the output of one line...
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7447870 |
Device for identifying data characteristics for flash memory
A highly efficient data characteristic identification device for flash memory is provided, including an instruction register, a plurality of auxiliary controllers, a data register, an address...
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7421564 |
Incrementing successive write operations to a plurality of memory devices
A centralized memory allocation system utilizes write pointer drift correction. The memory stores data units. The memory controller receives a write request associated with a data unit and stores...
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7421563 |
Hashing and serial decoding techniques
A technique for generating a list of all N-bit unsigned binary numbers by starting with an initial number less than some power of 2, successively multiplying the number by that power of 2 and...
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7409527 |
Bidirectional data storing method
A data storing method for a storage apparatus. The storage apparatus has a memory block, which includes a first terminal and a second terminal. The data storing method includes receiving a data...
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7404061 |
Permanent pool memory management method and system
A method, system, and computer program manager for a computing system memory in the operation of a computing process. At least one memory segment provides memory resources for the computing...
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7401202 |
Memory addressing
Addressing memory includes receiving a first operand to a memory addressing operator, receiving a second operand to the memory addressing operator, performing sign extension on the first operand to...
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7369135 |
Memory management system having a forward progress bit
A virtual memory system that maintains a list of pages that are required to be resident in a frame buffer to guarantee the eventual forward progress of a graphics application context running on a...
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7366882 |
Address calculation unit for an object oriented processor having differentiation circuitry for selectively operating micro-instructions
A processor is provided with a address calculation unit so as to generate addresses for elements of object oriented data structures in one processor clock cycle.
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7366872 |
Method for addressing configuration registers by scanning for a structure in configuration space and adding a known offset
A configuration memory space is scanned to locate an identification register whose value matches a predetermined value. The identification register identifies the location of a structure within the...
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7360040 |
Interleaver for iterative decoder
Interleaver for iterative decoder. A memory management scheme allows for single plane/single port memory devices to be used by the interleaver. The design is adaptable to soft-in soft-out (SISO)...
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7360039 |
Arrangements storing different versions of a set of data in separate memory areas and method for updating a set of data in a memory
Computer-readable medium storing a data structure for supporting persistant storage of a set of data, the data structure including: (a) at least an oldest version of the set of data in a first...
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7353356 |
High speed, low current consumption FIFO circuit
A FIFO circuit includes a write counter circuit, a memory circuit, a read counter circuit and a selector circuit. The write counter circuit counts a write clock signal during a valid period of...
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7330917 |
Decimation of fixed length queues having a number of position for holding data wherein new data is favored over old data
Decimation of data from a fixed length queue retaining a representative sample of the old data. Exponential decimation removes every nth sample. Dithered exponential decimation offsets the...
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7296124 |
Memory interface supporting multi-stream operation
A memory device includes one or more memory arrays and an interface controller for exchanging memory contents data with a semiconductor device over a communication link. The exchanging of data...
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7290118 |
Address control system for a memory storage device
A memory storage device having an address control system is disclosed. The memory storage device includes memory cells and an address control system configured to decode a bit number which...
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7290117 |
Memory having increased data-transfer speed and related systems and methods
A memory includes an address bus, address counter, address decoder, comparator, and control circuit. During a data read or write cycle, the address bus receives an external address, the address...
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7290084 |
Fast collision detection for a hashed content addressable memory (CAM) using a random access memory
A hardware hashing circuit is configured to perform a hashing function on a received character string, thereby creating a hashed output value and a collision resolution value. A content addressable...
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7287115 |
Multi-chip package type memory system
A multichip package type memory system is disclosed, which comprises a plurality of types of memory integrated circuits which are provided in a memory system in a package having an internal bus,...
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7266671 |
Register addressing
There is disclosed a technique for accessing a register file which comprises defining a first register address as a plurality of bits and using said first register address to access said register...
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7254670 |
System, method, and apparatus for realizing quicker access of an element in a data structure
This disclosure generally relates to a processor configured to access an element in a data structure. The processor includes an element in a data structure having an array, an index, and a base...
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7243209 |
Apparatus and method for speeding up access time of a large register file with wrap capability
An apparatus and method for speeding up access time of a large register file with wrap capability are provided. With the apparatus and method, the 2:1 multiplexers in conventional register file...
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7219218 |
Vector technique for addressing helper instruction groups associated with complex instructions
The present application describes a method and a system for executing instructions while reducing the logic required for execution in a processor. Instructions (e.g., atomic, integer-multiply,...
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7216215 |
Data access method applicable to various platforms
A data access method uses variable mask data and shift amount to write data into or read data from a data storage zone. The mask data and shift amount are determined according to starting and end...
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7206904 |
Method and system for buffering multiple requests from multiple devices to a memory
A system for sharing a computational resource by buffering multiple requests from multiple devices to a memory (e.g. a multi-port RAM or FIFO) in a single clock cycle. The system includes a memory...
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7185173 |
Column address path circuit and method for memory devices having a burst access mode
Column addresses are generated by a burst controller that includes respective latches for the three low-order bits of a column address. The two higher order bits of the latched address bits and...
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7181592 |
Pointer circuit
A pointer circuit for pointing to elements in at least one collection of elements comprises a base pointer for providing a first binary-coded value defining a first address of an element in the...
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7178005 |
Efficient implementation of timers in a multithreaded processor
A method and mechanism for managing timers in a multithreaded processing system. A storage device stores a plurality of count values corresponding to a plurality of timers. A read address generator...
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7177968 |
Data transmission system
In a data transmission system for carrying out data transmission/reception between a primary board and secondary boards by using a data transmission path, which employs a same signal line as an...
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7177421 |
Authentication engine architecture and method
Provided is an architecture (hardware implementation) for an authentication engine to increase the speed at which multi-loop and/or multi-round authentication algorithms may be performed on data...
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7165165 |
Anticipatory power control of memory
In a system in which individual memory banks may be under individual power control, a subsequent need for a memory bank that is currently in a low power state may be anticipated, so that the memory...
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7155596 |
Electronic device and playback control method therefor
There is provided an electronic device including: a storage medium in which content data is divided into units of clusters and stored; a link information table that records the link structure of...
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7152153 |
Bi-directional return register stack recovery from speculative execution of call/return upon branch misprediction
A Next Return Target Address stack to maintain return addresses for call and return operations. The invention accommodates both definite return addresses and speculative return address in a single...
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7139867 |
Partially-ordered cams used in ternary hierarchical address searching/sorting
An apparatus and method that utilizes partial ordering of ternary hierarchical addresses and their associated masks entries in both binary and ternary content addressable memories (CAMs) for...
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7133996 |
Memory device and internal control method therefor
A memory device for ensuring efficient access and reduction in current consumption. The memory device includes a plurality of memory cells arranged in accordance with a first address and a second...
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