Matches 151 - 200 out of 357 < 1 2 3 4 5 6 7 8 >
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6434686 Address generating circuit  
A write address counter counts a write clock WCK and determines output as a write address, while read address counter counts a read clock RCK and determines output as a read address. The position...
6430684 Processor circuits, systems, and methods with efficient granularity shift and/or merge instruction(s)  
A method of operating a processor ( 30 ). The method comprises a first step of fetching an instruction ( 20 ). The instruction includes an instruction opcode, a first data operand bit group...
6430671 Address generation utilizing an adder, a non-sequential counter and a latch  
An integrated circuit, e.g. an AC '97 conforming audio codec, includes a digital filter and gain module including multiple channels of gain control and multiple channels of digital filtering. A...
6430666 Linked list memory and method therefor  
A linked list memory ( 8 ) having an address generator ( 19 ) used during initial processing and a method for assigning addresses to lists corresponding to devices using a common memory ( 10 )....
6408374 Hashing method and apparatus  
A hashing method and apparatus uses a hash function that can be modified in real time by a hash control code. The hash function involves the combining together of multiple bit-shifted versions of a...
6405298 Linear address generator and method for generating a linear address using parallel computations and a single cycle algorithm  
A high-speed linear address generator (LAGEN) and method for generating a linear address are disclosed, which generator is operable to generate a linear address very quickly. In a preferred...
6405280 Packet-oriented synchronous DRAM interface supporting a plurality of orderings for data block transfers within a burst sequence  
A system and method for providing a burst sequence of data in a desired data ordering in response to a request packet. The burst sequence of data includes a plurality of data blocks and the request...
6401185 Method and apparatus for accessing paged objects using a fast division technique  
A fast division technique is provided to calculate the address of a slot in a paged object, when the slot is located on a different page than the beginning of the object. The fast division...
6381687 Flexible memory channel  
A memory channel means transferring data streams between different blocks and an internal memory means on a data chip, wherein said memory channel means comprises several memory channels. Each...
6374313 FIFO and method of operating same which inhibits output transitions when the last cell is read or when the FIFO is erased  
A FIFO is operated so no changes occur on an output thereof in response to (1) only one stage of the FIFO having a signal stored therein when a read command is supplied to the FIFO exclusively of a...
6374342 Translation lookaside buffer match detection using carry of lower side bit string of address addition  
There is disclosed DTLB in a microprocessor of the present invention, comprising an adder for adding a base address and a sign-extended offset address; a comparator for judging whether or not upper...
6370601 Intelligent direct memory access controller providing controlwise and datawise intelligence for DMA transfers  
The Intelligent DMA Controller (IDMAC) significantly reduces system latency by replacing one or more layers of software with hardware. The IDMAC uses controlwise and datawise intelligence. The...
6363473 Simulated memory stack in a stackless environment  
A computer system that simulates a memory stack in a non-general purpose register set in the computer's CPU. The computer system can use the simulated memory stack to store a return address before...
6360308 Buffer controller  
A method and apparatus for accessing successive memory locations without the need for multiple index register writes and without the need for a wide address bus from the controller into a memory...
6353874 Method and apparatus for controlling and caching memory read operations in a processing system  
A method and apparatus for controlling and caching memory read operations is presented. A memory structure is used to store data for read operations in a manner that allows the data to be reused in...
6345353 Stack pointer with post increment/decrement allowing selection from parallel read/write address outputs  
The stack pointer is used for generating the next unutilized location in the stack memory device in order to indicate where a current value in the program counter is to be written. The stack...
6336113 Data management method and data management apparatus  
A data management method is first used for registering the plurality of entry data having n-bit length and performing match retrieval by masking a (n−m(i)) bit from the least significant bit...
6334173 Combined cache with main memory and a control method thereof  
A combined cache with main memory and a control method thereof, which can be configured with various structures of cache by only adding a minimized control circuit in order to be used as main...
6321291 Method of measuring the speed of a memory unit in an integrated circuit  
In order to precisely measure the speed of memory unit, the memory unit stores at least one bit data at a predetermined bit position at each memory word such that the logical value of the one bit...
6321299 Computer circuits, systems, and methods using partial cache cleaning  
A method (50) of operating a computing system (10). The computing system comprises a cache memory (12b), and the cache memory has a predetermined number of cache lines. First, the method, for a...
6321320 Flexible and programmable BIST engine for on-chip memory array testing and characterization  
A highly flexible and complex BIST engine provides at-speed access, testing, characterization, and monitoring of on-chip memory arrays, independent of other chip circuitry such as a CPU core. Each...
6314507 Address generation unit  
An Address Generation Unit (AGU) for a processor such as Digital Signal Processor that includes a data memory addressable to obtain X and Y operands and a program decoder. The AGU is connected to...
6298429 Memory address generator capable of row-major and column-major sweeps  
An improved method and structure for generating addresses of a memory array facilitates the testing of a memory cell by generating the address of any adjacent memory cell to the memory cell under...
6282622 System, method, and program for detecting and assuring DRAM arrays  
A system, method, and program for detecting and assuring a row by column structure in a Dynamic Random Access Memory array is disclosed. By writing to and reading from each memory location of the...
6282700 Mechanism for maintaining revisions of objects in flash memory  
The inventive state mechanism assigns N+1 tags to N versions of an object stored in N memory areas. Thus, one tag is unused. An additional tag is used as a null or uninitialized tag. The other tags...
6279108 Programmable microcontroller architecture for disk drive system  
The software system architecture supports a rotating media in the storage and retrieval of data, where the rotating media stores in data tracks of multiple sectors, through the use of a...
6272590 Method and system for prefetching sequential data in a data storage system  
A method and system in a data storage system for reading stored data from the data storage system, where the data storage system comprises N data storage drives and an associated cache, where data...
6243799 Methods and apparatus for byte alignment operations for a memory device that stores an odd number of bytes  
A first-in-first-out (FIFO) memory device includes a plurality of FIFO memory cores that contain a plurality of cells. A variable cell size circuit supports user programmable cell sizes in a FIFO...
6226733 Address translation mechanism and method in a computer system  
An improved address translation method and mechanism for memory management in a computer system is disclosed. A fast physical address is generated in parallel with a fully computed...
6212615 Semiconductor circuit having burst counter circuit which is reduced the circuits passing from the clock input terminal to output terminal  
A semiconductor circuit of the present invention comprises, a decoder responding a plurality of address signals to produce a plurality of decoded address signals, a plurality of switch circuits...
6212601 Microprocessor system with block move circuit disposed between cache circuits  
In one embodiment, there is a single integrated circuit microprocessor (10). The microprocessor has an instruction pipeline (12) which comprises an execution stage (12a) operable to process an...
6209076 Method and apparatus for two-stage address generation  
The present invention is an apparatus and method for two-stage address generation that uses pipelining to avoid one level of latency in certain address-generation situations. The first level of the...
6205511 SDRAM address translator  
A buffer manager divides a memory space into a plurality of buffers. Each buffer occupies a plurality of sequential memory locations. The sequential memory locations include a start and an end...
6205531 Method and apparatus for virtual address translation  
A method and apparatus for efficiently translating virtual to physical addresses is provided. An embodiment of the apparatus includes a TLB descriptor table that includes a series of TLB...
6205539 Method for manipulating a stack pointer with post increment/decrement operation  
A method is provided for controlling a stack memory with a stack pointer. The method is composed of four major steps in a four phase instruction cycle. The first phase of the method decodes an...
6202106 Method for providing specific knowledge of a structure of parameter blocks to an intelligent direct memory access controller  
The Intelligent DMA Controller (IDMAC) significantly reduces system latency by replacing one or more layers of software with hardware. The IDMAC uses controlwise and datawise intelligence. The...
6202118 Apparatus for address translation to selectively improve data transfer rates on a disk storage device  
The overall transfer rate of user data is improved with the translation of certain low-number logical addresses into higher number physical addresses in order to displace inward the low-number...
6195737 Method and apparatus for relative addressing of tiled data  
The invention provides a method and apparatus that provides for a determination of a memory address for an object coordinate in a non-linear addressing scheme. To minimize computation complexity,...
6189086 Data processing apparatus  
A microprocessor apparatus executes a program including an instruction which indicates an address for taking out an operand from a main memory in a predetermined addressing mode which belongs to a...
6182207 Microcontroller with register system for the indirect accessing of internal memory via auxiliary register  
To accelerate read operations, or the operations that modify the operating parameters of a microcontroller, an interface is provided with three registers--an address register, an instruction and...
6178490 Method and device for the incremental reading of a memory  
Disclosed is a method and a device to improve the data output speed of a memory associated with a central processing unit of a microcomputer, should the reading be done at consecutive addresses of...
6173385 Address generator for solid state disk drive  
An address generator for a solid state disk drive device includes a hardware multiplier logic circuit dedicated to computation of the address by multiplying a lock size by a logical block number,...
6151667 Telecommunication device, more particularly, mobile radio terminal  
A telecommunication device has a processor for processing data and a memory which stores the data. The memory is coupled to the processor by a data bus and an address bus. A first address counter...
6148386 Address generator circuity for a circular buffer  
An improved apparatus and method for providing addresses for accessing circular memory buffers is provided. An apparatus comprised of a first feedback circuit, a second feedback circuit, a...
6148388 Extended page mode with memory address translation using a linear shift register  
The present disclosure concerns a method and apparatus for accessing a memory device, such as a dynamic random access memory (DRAM). The DRAM has a plurality of rows, wherein each row has a...
6141739 Memory Interface supporting access to memories using different data lengths  
A computing device (10) includes a processor (14) coupled to a memory interface (28). The memory interface (28) supports access to a variety of memories (12) using at least two different data...
6141740 Apparatus and method for microcode patching for generating a next address  
A superscalar microprocessor implements a microcode instruction unit that patches existing microcode instructions with substitute microcode instructions. A flag bit is associated with each line of...
6134629 Determining thresholds and wrap-around conditions in a first-in-first-out memory supporting a variety of read and write transaction sizes  
Data is read from a first-in-first-out (FIFO) queue. A first condition flag is generated which indicates whether a read transaction of a first transaction size may be performed. When a write...
6128692 Programming and verification address generation for random access memory blocks in programmable logic array integrated circuit devices  
A programmable logic array integrated circuit device has a relatively large block of programmable memory cells in addition to the usual programmable logic modules and the usual programmable...
6125433 Method of accomplishing a least-recently-used replacement scheme using ripple counters  
An optimized translation lookaside buffer (TLB) utilizes a least-recently-used algorithm for determining the replacement of virtual-to-physical memory translation entries. The TLB is faster and...
Matches 151 - 200 out of 357 < 1 2 3 4 5 6 7 8 >