Matches 101 - 150 out of 359 < 1 2 3 4 5 6 7 8 >
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6795873 Method and apparatus for a scheduling driver to implement a protocol utilizing time estimates for use with a device that does not generate interrupts  
The present invention provides a method and apparatus for a scheduling driver to implement a protocol using time estimates for use with a device that does not generate interrupts. An application...
6788617 Device for generating memory address and mobile station using the address for writing/reading data  
A device for generating memory addresses is provided that is suitable for generating memory addresses transposed in row/column directions with reference to a data successively stored therein along...
6785798 Method and system for circular addressing with efficient memory usage  
An apparatus generates addresses for circular address buffers in a memory, in which a higher boundary of a circular buffer is implied from the current address. This approach is applied alone, and...
6782467 Method and apparatus for fast limited core area access and cross-port word size multiplication in synchronous multiport memories  
An apparatus comprising a control circuit and a generation circuit. The control circuit may be configured to generate a mask signal, a unique counter control signal, and an incremented state signal...
6782447 Circular address register  
A device and corresponding programming instructions are provided that facilitate a circular addressing process. The device is configured to provide an address output that is constrained to lie...
6775758 Buffer page roll implementation for PCI-X block read transactions  
A computer system containing logic for processing a read block transaction from a PCI-X device. A technique is also disclosed for processing a read block transaction from a PCI-X device. The...
6775764 Search function for data lookup  
A SEARCH function preferably built into the instruction set of a microprocessor for quickly and efficiently searching a plurality of memory locations. Data from a significant number of memory...
6760830 Modulo addressing  
In one embodiment, a modulo addressing unit for a processor is described that includes a plurality of adders to generate an uncorrected target module address and at least one corrected target...
6754790 Method of accessing memory of de-interleaving unit  
A method is proposed for accessing the memory of a de-interleaving unit. The conventional access method has the drawback of ineffective use of the memory space of the de-interleaving unit, while...
6748509 Memory component with configurable multiple transfer formats  
A memory component, on a single integrated circuit, operated as a slave to an external master, includes a RAM, one or more configuration registers, data formatting logic, and associated control...
6745314 Circular buffer control circuit and method of operation thereof  
A circular buffer control circuit, a method of controlling a circular buffer and a digital signal processor (DSP) incorporating the circuit or the method. In one embodiment, the circuit includes:...
6732252 Memory interface device and memory address generation device  
A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including a plurality of output areas; and a control section for...
6725298 Method and system for filter-processing by ensuring a memory space for a ring-buffer in digital signal processor  
A method of managing ring-buffer memory space in a digital signal processor when processing a filter, includes releasing ring-buffer memory space previously reserved for ring-buffer data upon...
6721867 Memory processing in a microprocessor  
The invention relates to memory processing in a microprocessor. The microprocessor comprises a memory indicated by means of alignment boundaries for storing data, at least one register for storing...
6711494 Data formatter for shifting data to correct data lanes  
A data formatter includes a shift register and a pointer manager. The shift register receives data from a providing RAM and shifts that data in response to reading data from the providing RAM and...
6708264 Synchronous memory device with prefetch address counter  
A synchronous memory device includes a prefetch address counter. The address counter is composed of an n number of one-bit counter circuits, an n number of adders to which the output signals of...
6701422 Memory control system with incrementer for generating speculative addresses  
A memory controller includes an incrementer for predicting a next address to be asserted by a processor. The incrementer, structurally a counter, is configurable to wrap at a wrap boundary and to...
6701423 High speed address sequencer  
An address sequencer circuit for generating addresses for accessing a memory device. The address sequencer includes a plurality of address stages that are coupled together, and also includes a...
6694420 Address range checking circuit and method of operation  
An address range checking circuit capable of determining if a target address, A[M:0], is within an address space having 2 N address locations beginning at a base address location, B[M:0], is...
6687782 Method and implementation for addressing and accessing an expanded read only memory (ROM)  
A ROM is provided with sufficient input address terminals for receipt of a unique address for each data storage location, even though the number of ROM input addresses exceeds the capacity of the...
6684315 Method and system for supporting multiprocessor TLB-purge instructions using directed write transactions  
A method and system for purging translation lookaside buffers (TLB) of a computer system are described. Directed write transactions can be used to avoid deadlock and avoid the need for additional...
6681313 Method and system for fast access to a translation lookaside buffer  
In a system for conducting virtual address translation in a virtual memory system and implementing a table such as a Translation Lookaside Buffer, a system and method enabling quicker access to...
6678816 Method for optimized representation of page table entries  
Method for producing a predetermined length page memory pointer record, according to a selected page size and a selected page address, the method including the procedures of: determining a dynamic...
6670895 Method and apparatus for swapping the contents of address registers  
Methods and apparatus are provided for use in digital information processors that support digital memory buffers. In one aspect of the present invention, a digital signal processor receives a swap...
6665768 Table look-up operation for SIMD processors with interleaved memory systems  
An apparatus and method for accessing data in a processing system are described. The system includes multiple processing elements for executing program instructions. The processing system can be a...
6654871 Device and a method for performing stack operations in a processing system  
A method and a device for performing stack operations within a processing system. A first and second stack pointers point to a top of a stack and to a memory location following the top of the...
6647484 Transpose address mode in general purpose DSP processor  
The present invention provides a register-indirect addressing mode using modulo arithmetic to transpose addresses for digital processing systems. The preferred systems and methods permit direct...
6643761 Address generation unit and digital signal processor (DSP) including a digital addressing unit for performing selected addressing operations  
An address generation unit (AGU) and a digital signal processor (DSP) including such an AGU are disclosed. The AGU ( 3 ) has a register file ( 4 ) providing order (R), stage (S), and displacement...
6633966 FIFO memory having reduced scale  
FIFO type memory is provided on a small circuit scale. Reading of data Dout<3:0> from a two-port type RAM (101) is executed with respect to the address specified by a read address ( 21 ) in...
6629190 Non-redundant nonvolatile memory and method for sequentially accessing the nonvolatile memory using shift registers to selectively bypass individual word lines  
A memory including a plurality of memory word lines and a sequential addressing circuit is provided. The sequential addressing circuit comprises at least one sequential shift register including at...
6622232 Apparatus and method for performing non-aligned memory accesses  
A memory that supports non-aligned memory accesses includes a field address generator circuit, multiple field memories, and a data rotation circuit. The field address generator circuit generates...
6611894 Data retrieval apparatus  
The present invention relates to a data retrieval apparatus for retrieving the data from a number of places of data stored in memories which adopts binary search method and enables high-speed...
6604184 Virtual memory mapping using region-based page tables  
The present invention is a method and apparatus to map virtual memory space. A region register file provides a region identifier for a virtual address in the virtual memory space. The virtual...
6601158 Count/address generation circuitry  
According to one embodiment of the invention, an apparatus that includes a first and second counter both including a count computation circuit and an upper bound circuit. The output of the upper...
6581149 Data carrier having address mode or command extension capability  
A data carrier is disclosed for the communication of transmission information to a communication station. In particular, the data carrier includes a program memory for storing a program code...
6574707 Memory interface protocol using two addressing modes and method of operation  
A memory interface ( 15 ) and method of use implements a cache ( 14 ) bursting addressing technique which begins a read of main memory ( 16 ) in a wrap around mode before automatically switching...
6574722 Semiconductor storage device  
If a word line is selected by inputting an immediate value and base address, whose values are determined at different timings, to an adder, the access speed decreases due to the constraint of the...
6571327 Non-aligned double word access in word addressable memory  
An apparatus which generates even addressed words and odd addressed words in a memory. The apparatus consists of a port adapted for receiving an address, one or more even units in operative...
6560691 Modulus address generator and method for determining a modulus address  
A modulus address generator calculates the next address to access from a current address of a circular buffer having a length L and an address shift from the current address to the next address to...
6560696 Return register stack target predictor  
A Next Return Target Address stack to maintain return addresses for call and return operations. The invention accommodates both definite return addresses and speculative return address in a single...
6553474 Data processor changing an alignment of loaded data  
A data processor in which a read operation, including misaligned data as operand data, can be performed in a single cycle. An alignment buffer having a register to hold data stored at one address...
6542985 Event counter  
A data processor is disclosed that executes a number of microcode instruction words. Each of the microcode instruction words has a bit field reserved to indicate which, if any, event counters are...
6542980 Time slot data memory storage and access system  
A memory access system maps a block of data between a time stamp and an addressable memory location in a manner which mimics actual transmission slot timing. The system includes a slot time module,...
6539467 Microprocessor with non-aligned memory access  
A data processing system ( 1300 ) is provided with a digital signal processor (DSP) ( 1301 ) that has an instruction set architecture (ISA) that is optimized for intensive numeric algorithm...
6532529 Microcomputer including flash memory overwritable during operation and operating method thereof  
A microcomputer includes a flash memory, a central processing unit, a plurality of storage devices, and an address predecoder. The predecoder is configured to switch between a first memory mapping...
6523105 Recording medium control device and method  
An information recording/reproducing device includes a transfer control section for carrying out input/output of transfer data, a recording medium control section for carrying out writing...
6519692 Method for updating a pointer to access a memory address in a DSP  
A processor coupled to a memory for providing a pointer in order to access a corresponding memory address, the pointer being updated by adding a predetermined increment according to logic integral...
6516401 Data reading method and data reading apparatus  
The present invention provides, at a lower cost, a highly reliable data reading method and data reading apparatus that can improve backward sequential reading performance. The disk drive is...
6480942 Synchronized FIFO memory circuit  
A synchronized FIFO memory circuit includes a random access memory and a FIFO controller having a decreased critical-path length. The synchronized FIFO circuit comprises a first counter for...
6457114 Asynchronous memory interface for a video processor with a 2N sized buffer and N&plus 1 wide bit gray coded counters  
A memory controller for a special purpose digital video processor. To achieve a speed enhancement when using multiple bank memory such as SDRAM, the memory controller arbitrates requests for access...
Matches 101 - 150 out of 359 < 1 2 3 4 5 6 7 8 >